forked from Github_Repos/cvw
264 lines
14 KiB
Tcl
264 lines
14 KiB
Tcl
# The main clocks are all autogenerated by the Xilinx IP
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# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus.
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# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
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# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
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create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
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##### GPI ####
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set_property PACKAGE_PIN E34 [get_ports {GPI[0]}]
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set_property PACKAGE_PIN M22 [get_ports {GPI[1]}]
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set_property PACKAGE_PIN AW27 [get_ports {GPI[2]}]
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set_property PACKAGE_PIN A10 [get_ports {GPI[3]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPI[2]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
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set_max_delay -from [get_ports {GPI[*]}] 10.000
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##### GPO ####
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set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}]
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set_property PACKAGE_PIN AV34 [get_ports {GPO[1]}]
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set_property PACKAGE_PIN AY30 [get_ports {GPO[2]}]
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set_property PACKAGE_PIN BF32 [get_ports {GPO[4]}]
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set_property PACKAGE_PIN BB32 [get_ports {GPO[3]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[4]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}]
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set_max_delay -to [get_ports {GPO[*]}] 10.000
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}]
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##### UART #####
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set_property PACKAGE_PIN BC24 [get_ports UARTSin]
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set_property PACKAGE_PIN BE24 [get_ports UARTSout]
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set_max_delay -from [get_ports UARTSin] 10.000
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set_max_delay -to [get_ports UARTSout] 10.000
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set_property IOSTANDARD LVCMOS18 [get_ports UARTSin]
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set_property IOSTANDARD LVCMOS18 [get_ports UARTSout]
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# set_property DRIVE 6 [get_ports UARTSout]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin]
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports UARTSout]
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##### reset #####
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set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -min -add_delay 2.000 [get_ports reset]
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set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -max -add_delay 2.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
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set_max_delay -from [get_ports reset] 15.000
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set_false_path -from [get_ports reset]
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set_property PACKAGE_PIN E34 [get_ports {reset}]
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set_property IOSTANDARD LVCMOS12 [get_ports {reset}]
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##### cpu_reset #####
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set_property PACKAGE_PIN AY35 [get_ports {cpu_reset}]
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set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]
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##### calib #####
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set_property PACKAGE_PIN BA37 [get_ports calib]
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set_property IOSTANDARD LVCMOS12 [get_ports calib]
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
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set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000
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##### ahblite_resetn #####
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set_property PACKAGE_PIN AV36 [get_ports {ahblite_resetn}]
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set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {ahblite_resetn}]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {ahblite_resetn}]
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##### south_rst #####
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set_property PACKAGE_PIN D9 [get_ports south_rst]
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set_property IOSTANDARD LVCMOS12 [get_ports south_rst]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports south_rst]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports south_rst]
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##### SD Card I/O #####
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set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}]
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set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}]
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set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}]
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set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}]
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set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK]
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set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}]
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set_property PACKAGE_PIN BB16 [get_ports SDCCLK]
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set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}]
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set_property PULLUP true [get_ports {SDCDat[3]}]
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set_property PULLUP true [get_ports {SDCDat[2]}]
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set_property PULLUP true [get_ports {SDCDat[1]}]
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set_property PULLUP true [get_ports {SDCDat[0]}]
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set_property PULLUP true [get_ports {SDCCmd}]
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set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
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set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
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set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
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set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
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set_property DCI_CASCADE {64} [get_iobanks 65]
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set_property INTERNAL_VREF 0.9 [get_iobanks 65]
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set_property PACKAGE_PIN E33 [get_ports c0_ddr4_act_n]
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set_property PACKAGE_PIN C30 [get_ports {c0_ddr4_adr[0]}]
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set_property PACKAGE_PIN A31 [get_ports {c0_ddr4_adr[10]}]
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set_property PACKAGE_PIN A33 [get_ports {c0_ddr4_adr[11]}]
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set_property PACKAGE_PIN F29 [get_ports {c0_ddr4_adr[12]}]
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set_property PACKAGE_PIN B32 [get_ports {c0_ddr4_adr[13]}]
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set_property PACKAGE_PIN D29 [get_ports {c0_ddr4_adr[14]}]
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set_property PACKAGE_PIN B31 [get_ports {c0_ddr4_adr[15]}]
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set_property PACKAGE_PIN B33 [get_ports {c0_ddr4_adr[16]}]
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set_property PACKAGE_PIN D32 [get_ports {c0_ddr4_adr[1]}]
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set_property PACKAGE_PIN B30 [get_ports {c0_ddr4_adr[2]}]
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set_property PACKAGE_PIN C33 [get_ports {c0_ddr4_adr[3]}]
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set_property PACKAGE_PIN E32 [get_ports {c0_ddr4_adr[4]}]
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set_property PACKAGE_PIN A29 [get_ports {c0_ddr4_adr[5]}]
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set_property PACKAGE_PIN C29 [get_ports {c0_ddr4_adr[6]}]
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set_property PACKAGE_PIN E29 [get_ports {c0_ddr4_adr[7]}]
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set_property PACKAGE_PIN A30 [get_ports {c0_ddr4_adr[8]}]
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set_property PACKAGE_PIN C32 [get_ports {c0_ddr4_adr[9]}]
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set_property PACKAGE_PIN G30 [get_ports {c0_ddr4_ba[0]}]
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set_property PACKAGE_PIN F30 [get_ports {c0_ddr4_ba[1]}]
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set_property PACKAGE_PIN F33 [get_ports {c0_ddr4_bg[0]}]
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set_property PACKAGE_PIN E31 [get_ports {c0_ddr4_ck_t[0]}]
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set_property PACKAGE_PIN D31 [get_ports {c0_ddr4_ck_c[0]}]
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set_property PACKAGE_PIN K29 [get_ports {c0_ddr4_cke[0]}]
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set_property PACKAGE_PIN D30 [get_ports {c0_ddr4_cs_n[0]}]
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set_property PACKAGE_PIN J37 [get_ports {c0_ddr4_dq[0]}]
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set_property PACKAGE_PIN F35 [get_ports {c0_ddr4_dq[10]}]
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set_property PACKAGE_PIN J35 [get_ports {c0_ddr4_dq[11]}]
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set_property PACKAGE_PIN G37 [get_ports {c0_ddr4_dq[12]}]
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set_property PACKAGE_PIN H35 [get_ports {c0_ddr4_dq[13]}]
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set_property PACKAGE_PIN G36 [get_ports {c0_ddr4_dq[14]}]
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set_property PACKAGE_PIN H37 [get_ports {c0_ddr4_dq[15]}]
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set_property PACKAGE_PIN C39 [get_ports {c0_ddr4_dq[16]}]
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set_property PACKAGE_PIN A38 [get_ports {c0_ddr4_dq[17]}]
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set_property PACKAGE_PIN B40 [get_ports {c0_ddr4_dq[18]}]
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set_property PACKAGE_PIN D40 [get_ports {c0_ddr4_dq[19]}]
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set_property PACKAGE_PIN H40 [get_ports {c0_ddr4_dq[1]}]
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set_property PACKAGE_PIN E38 [get_ports {c0_ddr4_dq[20]}]
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set_property PACKAGE_PIN B38 [get_ports {c0_ddr4_dq[21]}]
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set_property PACKAGE_PIN E37 [get_ports {c0_ddr4_dq[22]}]
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set_property PACKAGE_PIN C40 [get_ports {c0_ddr4_dq[23]}]
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set_property PACKAGE_PIN C34 [get_ports {c0_ddr4_dq[24]}]
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set_property PACKAGE_PIN A34 [get_ports {c0_ddr4_dq[25]}]
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set_property PACKAGE_PIN D34 [get_ports {c0_ddr4_dq[26]}]
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set_property PACKAGE_PIN A35 [get_ports {c0_ddr4_dq[27]}]
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set_property PACKAGE_PIN A36 [get_ports {c0_ddr4_dq[28]}]
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set_property PACKAGE_PIN C35 [get_ports {c0_ddr4_dq[29]}]
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set_property PACKAGE_PIN F38 [get_ports {c0_ddr4_dq[2]}]
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set_property PACKAGE_PIN B35 [get_ports {c0_ddr4_dq[30]}]
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set_property PACKAGE_PIN D35 [get_ports {c0_ddr4_dq[31]}]
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set_property PACKAGE_PIN N27 [get_ports {c0_ddr4_dq[32]}]
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set_property PACKAGE_PIN R27 [get_ports {c0_ddr4_dq[33]}]
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set_property PACKAGE_PIN N24 [get_ports {c0_ddr4_dq[34]}]
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set_property PACKAGE_PIN R24 [get_ports {c0_ddr4_dq[35]}]
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set_property PACKAGE_PIN P24 [get_ports {c0_ddr4_dq[36]}]
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set_property PACKAGE_PIN P26 [get_ports {c0_ddr4_dq[37]}]
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set_property PACKAGE_PIN P27 [get_ports {c0_ddr4_dq[38]}]
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set_property PACKAGE_PIN T24 [get_ports {c0_ddr4_dq[39]}]
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set_property PACKAGE_PIN H39 [get_ports {c0_ddr4_dq[3]}]
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set_property PACKAGE_PIN K27 [get_ports {c0_ddr4_dq[40]}]
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set_property PACKAGE_PIN L26 [get_ports {c0_ddr4_dq[41]}]
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set_property PACKAGE_PIN J27 [get_ports {c0_ddr4_dq[42]}]
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set_property PACKAGE_PIN K28 [get_ports {c0_ddr4_dq[43]}]
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set_property PACKAGE_PIN K26 [get_ports {c0_ddr4_dq[44]}]
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set_property PACKAGE_PIN M25 [get_ports {c0_ddr4_dq[45]}]
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set_property PACKAGE_PIN J26 [get_ports {c0_ddr4_dq[46]}]
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set_property PACKAGE_PIN L28 [get_ports {c0_ddr4_dq[47]}]
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set_property PACKAGE_PIN E27 [get_ports {c0_ddr4_dq[48]}]
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set_property PACKAGE_PIN E28 [get_ports {c0_ddr4_dq[49]}]
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set_property PACKAGE_PIN K37 [get_ports {c0_ddr4_dq[4]}]
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set_property PACKAGE_PIN E26 [get_ports {c0_ddr4_dq[50]}]
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set_property PACKAGE_PIN H27 [get_ports {c0_ddr4_dq[51]}]
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set_property PACKAGE_PIN F25 [get_ports {c0_ddr4_dq[52]}]
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set_property PACKAGE_PIN F28 [get_ports {c0_ddr4_dq[53]}]
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set_property PACKAGE_PIN G25 [get_ports {c0_ddr4_dq[54]}]
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set_property PACKAGE_PIN G27 [get_ports {c0_ddr4_dq[55]}]
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set_property PACKAGE_PIN B28 [get_ports {c0_ddr4_dq[56]}]
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set_property PACKAGE_PIN A28 [get_ports {c0_ddr4_dq[57]}]
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set_property PACKAGE_PIN B25 [get_ports {c0_ddr4_dq[58]}]
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set_property PACKAGE_PIN B27 [get_ports {c0_ddr4_dq[59]}]
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set_property PACKAGE_PIN G40 [get_ports {c0_ddr4_dq[5]}]
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set_property PACKAGE_PIN D25 [get_ports {c0_ddr4_dq[60]}]
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set_property PACKAGE_PIN C27 [get_ports {c0_ddr4_dq[61]}]
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set_property PACKAGE_PIN C25 [get_ports {c0_ddr4_dq[62]}]
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set_property PACKAGE_PIN D26 [get_ports {c0_ddr4_dq[63]}]
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set_property PACKAGE_PIN F39 [get_ports {c0_ddr4_dq[6]}]
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set_property PACKAGE_PIN F40 [get_ports {c0_ddr4_dq[7]}]
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set_property PACKAGE_PIN F36 [get_ports {c0_ddr4_dq[8]}]
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set_property PACKAGE_PIN J36 [get_ports {c0_ddr4_dq[9]}]
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set_property PACKAGE_PIN H38 [get_ports {c0_ddr4_dqs_t[0]}]
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set_property PACKAGE_PIN G38 [get_ports {c0_ddr4_dqs_c[0]}]
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set_property PACKAGE_PIN H34 [get_ports {c0_ddr4_dqs_t[1]}]
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set_property PACKAGE_PIN G35 [get_ports {c0_ddr4_dqs_c[1]}]
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set_property PACKAGE_PIN A39 [get_ports {c0_ddr4_dqs_t[2]}]
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set_property PACKAGE_PIN A40 [get_ports {c0_ddr4_dqs_c[2]}]
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set_property PACKAGE_PIN B36 [get_ports {c0_ddr4_dqs_t[3]}]
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set_property PACKAGE_PIN B37 [get_ports {c0_ddr4_dqs_c[3]}]
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set_property PACKAGE_PIN P25 [get_ports {c0_ddr4_dqs_t[4]}]
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set_property PACKAGE_PIN N25 [get_ports {c0_ddr4_dqs_c[4]}]
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set_property PACKAGE_PIN L24 [get_ports {c0_ddr4_dqs_t[5]}]
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set_property PACKAGE_PIN L25 [get_ports {c0_ddr4_dqs_c[5]}]
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set_property PACKAGE_PIN H28 [get_ports {c0_ddr4_dqs_t[6]}]
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set_property PACKAGE_PIN G28 [get_ports {c0_ddr4_dqs_c[6]}]
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set_property PACKAGE_PIN B26 [get_ports {c0_ddr4_dqs_t[7]}]
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set_property PACKAGE_PIN A26 [get_ports {c0_ddr4_dqs_c[7]}]
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set_property PACKAGE_PIN J31 [get_ports {c0_ddr4_odt[0]}]
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set_property PACKAGE_PIN M28 [get_ports c0_ddr4_reset_n]
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set_property PACKAGE_PIN J39 [get_ports {c0_ddr4_dm_dbi_n[0]}]
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set_property PACKAGE_PIN F34 [get_ports {c0_ddr4_dm_dbi_n[1]}]
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set_property PACKAGE_PIN E39 [get_ports {c0_ddr4_dm_dbi_n[2]}]
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set_property PACKAGE_PIN D37 [get_ports {c0_ddr4_dm_dbi_n[3]}]
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set_property PACKAGE_PIN T26 [get_ports {c0_ddr4_dm_dbi_n[4]}]
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set_property PACKAGE_PIN M27 [get_ports {c0_ddr4_dm_dbi_n[5]}]
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set_property PACKAGE_PIN G26 [get_ports {c0_ddr4_dm_dbi_n[6]}]
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set_property PACKAGE_PIN D27 [get_ports {c0_ddr4_dm_dbi_n[7]}]
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set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
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set_max_delay -from [get_pins {xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C}] -to [get_ports c0_ddr4_reset_n] 50.000
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