forked from Github_Repos/cvw
54 lines
2.2 KiB
ArmAsm
54 lines
2.2 KiB
ArmAsm
///////////////////////////////////////////
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//
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// WALLY-MIE
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//
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// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
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//
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// Created 2022-04-10
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "WALLY-TEST-LIB-64.h"
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INIT_TESTS
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CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
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TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
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li x28, 0x8
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csrs mstatus, x28 // set mstatus.MIE bit to 1.
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WRITE_READ_CSR mie, 0x0 // force zeroing out mie CSR.
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// test 5.3.1.6 Interrupt enabling and priority tests
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// testing with MIE bits set already tested in WALLY-trap
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// note that none of these interrupts should be caught or handled.
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jal cause_s_soft_interrupt
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jal cause_m_soft_interrupt
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jal cause_s_time_interrupt
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jal cause_m_time_interrupt
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li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
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// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
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jal cause_s_ext_interrupt_GPIO
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li a3, 0x40
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jal cause_m_ext_interrupt
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END_TESTS
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TEST_STACK_AND_DATA
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