forked from Github_Repos/cvw
532 lines
18 KiB
ArmAsm
532 lines
18 KiB
ArmAsm
// -----------
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// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
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// version : 0.5.1
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// timestamp : Mon Aug 2 08:58:53 2021 GMT
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// usage : riscv_ctg \
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// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
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// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
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// --base-isa rv32e \
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// --randomize
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// -----------
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//
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// -----------
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// Copyright (c) 2020. RISC-V International. All rights reserved.
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the sra instruction of the RISC-V E extension for the sra covergroup.
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//
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#define RVTEST_E
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV32E")
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",sra)
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RVTEST_SIGBASE( x3,signature_x3_1)
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inst_0:
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// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x11, rs2==x9, rd==x12, rs1_val < 0 and rs2_val == 0, rs1_val == -1431655766, rs1_val==-1431655766
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// opcode: sra ; op1:x11; op2:x9; dest:x12; op1val:-0x55555556; op2val:0x0
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TEST_RR_OP(sra, x12, x11, x9, -0x55555556, -0x55555556, 0x0, x3, 0, x5)
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inst_1:
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// rs1 == rd != rs2, rs1==x8, rs2==x12, rd==x8, rs2_val == 15, rs1_val == -524289, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen
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// opcode: sra ; op1:x8; op2:x12; dest:x8; op1val:-0x80001; op2val:0xf
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TEST_RR_OP(sra, x8, x8, x12, -0x11, -0x80001, 0xf, x3, 4, x5)
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inst_2:
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// rs2 == rd != rs1, rs1==x10, rs2==x2, rd==x2, rs2_val == 23, rs1_val==3, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen
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// opcode: sra ; op1:x10; op2:x2; dest:x2; op1val:0x3; op2val:0x17
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TEST_RR_OP(sra, x2, x10, x2, 0x0, 0x3, 0x17, x3, 8, x5)
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inst_3:
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// rs1 == rs2 != rd, rs1==x6, rs2==x6, rd==x4, rs2_val == 27,
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// opcode: sra ; op1:x6; op2:x6; dest:x4; op1val:-0x8; op2val:-0x8
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TEST_RR_OP(sra, x4, x6, x6, -0x1, -0x8, -0x8, x3, 12, x5)
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inst_4:
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// rs1 == rs2 == rd, rs1==x13, rs2==x13, rd==x13, rs2_val == 29, rs1_val==-1431655765
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// opcode: sra ; op1:x13; op2:x13; dest:x13; op1val:-0x55555555; op2val:-0x55555555
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TEST_RR_OP(sra, x13, x13, x13, -0xaaaab, -0x55555555, -0x55555555, x3, 16, x5)
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inst_5:
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// rs1==x0, rs2==x10, rd==x7, rs2_val == 30, rs1_val == 16384
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// opcode: sra ; op1:x0; op2:x10; dest:x7; op1val:0x0; op2val:0x1e
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TEST_RR_OP(sra, x7, x0, x10, 0x0, 0x0, 0x1e, x3, 20, x5)
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inst_6:
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// rs1==x1, rs2==x15, rd==x14, rs1_val == 2147483647, rs2_val == 21, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen
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// opcode: sra ; op1:x1; op2:x15; dest:x14; op1val:0x7fffffff; op2val:0x15
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TEST_RR_OP(sra, x14, x1, x15, 0x3ff, 0x7fffffff, 0x15, x3, 24, x5)
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RVTEST_SIGBASE( x4,signature_x4_0)
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inst_7:
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// rs1==x3, rs2==x7, rd==x5, rs1_val == -1073741825, rs2_val == 1
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// opcode: sra ; op1:x3; op2:x7; dest:x5; op1val:-0x40000001; op2val:0x1
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TEST_RR_OP(sra, x5, x3, x7, -0x20000001, -0x40000001, 0x1, x4, 0, x6)
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inst_8:
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// rs1==x2, rs2==x8, rd==x15, rs1_val == -536870913,
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// opcode: sra ; op1:x2; op2:x8; dest:x15; op1val:-0x20000001; op2val:0x7
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TEST_RR_OP(sra, x15, x2, x8, -0x400001, -0x20000001, 0x7, x4, 4, x6)
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inst_9:
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// rs1==x7, rs2==x11, rd==x1, rs1_val == -268435457,
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// opcode: sra ; op1:x7; op2:x11; dest:x1; op1val:-0x10000001; op2val:0x9
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TEST_RR_OP(sra, x1, x7, x11, -0x80001, -0x10000001, 0x9, x4, 8, x6)
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inst_10:
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// rs1==x12, rs2==x0, rd==x9, rs1_val == -134217729,
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// opcode: sra ; op1:x12; op2:x0; dest:x9; op1val:-0x8000001; op2val:0x0
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TEST_RR_OP(sra, x9, x12, x0, -0x8000001, -0x8000001, 0x0, x4, 12, x6)
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inst_11:
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// rs1==x5, rs2==x14, rd==x10, rs1_val == -67108865,
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// opcode: sra ; op1:x5; op2:x14; dest:x10; op1val:-0x4000001; op2val:0x17
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TEST_RR_OP(sra, x10, x5, x14, -0x9, -0x4000001, 0x17, x4, 16, x6)
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RVTEST_SIGBASE( x2,signature_x2_0)
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inst_12:
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// rs1==x4, rs2==x5, rd==x0, rs1_val == -33554433,
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// opcode: sra ; op1:x4; op2:x5; dest:x0; op1val:-0x2000001; op2val:0x9
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TEST_RR_OP(sra, x0, x4, x5, 0, -0x2000001, 0x9, x2, 0, x7)
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inst_13:
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// rs1==x15, rs2==x4, rd==x3, rs1_val == -16777217,
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// opcode: sra ; op1:x15; op2:x4; dest:x3; op1val:-0x1000001; op2val:0xe
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TEST_RR_OP(sra, x3, x15, x4, -0x401, -0x1000001, 0xe, x2, 4, x7)
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inst_14:
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// rs1==x9, rs2==x3, rd==x11, rs1_val == -8388609,
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// opcode: sra ; op1:x9; op2:x3; dest:x11; op1val:-0x800001; op2val:0x11
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TEST_RR_OP(sra, x11, x9, x3, -0x41, -0x800001, 0x11, x2, 8, x7)
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inst_15:
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// rs1==x14, rs2==x1, rd==x6, rs1_val == -4194305,
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// opcode: sra ; op1:x14; op2:x1; dest:x6; op1val:-0x400001; op2val:0x1b
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TEST_RR_OP(sra, x6, x14, x1, -0x1, -0x400001, 0x1b, x2, 12, x7)
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inst_16:
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// rs1_val == -2097153,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x200001; op2val:0xf
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TEST_RR_OP(sra, x12, x10, x11, -0x41, -0x200001, 0xf, x2, 16, x7)
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inst_17:
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// rs1_val == -1048577, rs2_val == 2
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x100001; op2val:0x2
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TEST_RR_OP(sra, x12, x10, x11, -0x40001, -0x100001, 0x2, x2, 20, x1)
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inst_18:
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// rs1_val == -262145,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x40001; op2val:0x9
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TEST_RR_OP(sra, x12, x10, x11, -0x201, -0x40001, 0x9, x2, 24, x1)
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inst_19:
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// rs1_val == -131073,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x20001; op2val:0x1e
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x20001, 0x1e, x2, 28, x1)
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inst_20:
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// rs1_val == -65537, rs2_val == 16
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x10001; op2val:0x10
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TEST_RR_OP(sra, x12, x10, x11, -0x2, -0x10001, 0x10, x2, 32, x1)
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inst_21:
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// rs1_val == -32769,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x8001; op2val:0x1b
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x8001, 0x1b, x2, 36, x1)
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inst_22:
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// rs1_val == -16385,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x4001; op2val:0x2
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TEST_RR_OP(sra, x12, x10, x11, -0x1001, -0x4001, 0x2, x2, 40, x1)
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inst_23:
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// rs1_val == -8193,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2001; op2val:0x1e
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x2001, 0x1e, x2, 44, x1)
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inst_24:
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// rs1_val == -4097,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x1001; op2val:0xf
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x1001, 0xf, x2, 48, x1)
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inst_25:
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// rs1_val == -2049,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x801; op2val:0x12
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x801, 0x12, x2, 52, x1)
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inst_26:
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// rs1_val == -1025,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x401; op2val:0x12
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x401, 0x12, x2, 56, x1)
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inst_27:
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// rs1_val == -513,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x201; op2val:0x1b
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x201, 0x1b, x2, 60, x1)
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inst_28:
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// rs1_val == -257,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x101; op2val:0x9
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x101, 0x9, x2, 64, x1)
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inst_29:
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// rs1_val == -129,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x81; op2val:0x6
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TEST_RR_OP(sra, x12, x10, x11, -0x3, -0x81, 0x6, x2, 68, x1)
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inst_30:
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// rs1_val == -65,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x41; op2val:0x1d
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x41, 0x1d, x2, 72, x1)
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inst_31:
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// rs1_val == -33, rs2_val == 8
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x21; op2val:0x8
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x21, 0x8, x2, 76, x1)
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inst_32:
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// rs1_val == -17,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x11; op2val:0xe
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x11, 0xe, x2, 80, x1)
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inst_33:
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// rs1_val == -9,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x9; op2val:0x9
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x9, 0x9, x2, 84, x1)
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inst_34:
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// rs1_val == -5,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x5; op2val:0xe
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x5, 0xe, x2, 88, x1)
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inst_35:
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// rs1_val == -3,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x3; op2val:0x15
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x3, 0x15, x2, 92, x1)
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inst_36:
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// rs1_val == -2,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2; op2val:0x10
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TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x2, 0x10, x2, 96, x1)
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inst_37:
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// rs2_val == 4, rs1_val==2, rs1_val == 2
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2; op2val:0x4
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TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x2, 0x4, x2, 100, x1)
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inst_38:
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// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000; op2val:0x13
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TEST_RR_OP(sra, x12, x10, x11, -0x1000, -0x80000000, 0x13, x2, 104, x1)
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inst_39:
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// rs1_val == 1073741824,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40000000; op2val:0x1b
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TEST_RR_OP(sra, x12, x10, x11, 0x8, 0x40000000, 0x1b, x2, 108, x1)
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inst_40:
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// rs1_val == 536870912,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20000000; op2val:0x9
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TEST_RR_OP(sra, x12, x10, x11, 0x100000, 0x20000000, 0x9, x2, 112, x1)
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inst_41:
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// rs1_val == 268435456,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10000000; op2val:0xb
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TEST_RR_OP(sra, x12, x10, x11, 0x20000, 0x10000000, 0xb, x2, 116, x1)
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inst_42:
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// rs1_val == 134217728,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8000000; op2val:0x17
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TEST_RR_OP(sra, x12, x10, x11, 0x10, 0x8000000, 0x17, x2, 120, x1)
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inst_43:
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// rs1_val == 67108864,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4000000; op2val:0xc
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TEST_RR_OP(sra, x12, x10, x11, 0x4000, 0x4000000, 0xc, x2, 124, x1)
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inst_44:
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// rs1_val == 33554432,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2000000; op2val:0x11
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TEST_RR_OP(sra, x12, x10, x11, 0x100, 0x2000000, 0x11, x2, 128, x1)
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inst_45:
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// rs1_val == 16777216,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1000000; op2val:0x11
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TEST_RR_OP(sra, x12, x10, x11, 0x80, 0x1000000, 0x11, x2, 132, x1)
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inst_46:
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// rs1_val == 8388608, rs1_val > 0 and rs2_val == 0
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x800000; op2val:0x0
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TEST_RR_OP(sra, x12, x10, x11, 0x800000, 0x800000, 0x0, x2, 136, x1)
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inst_47:
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// rs1_val == 4194304,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x400000; op2val:0xb
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TEST_RR_OP(sra, x12, x10, x11, 0x800, 0x400000, 0xb, x2, 140, x1)
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inst_48:
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// rs1_val == 2097152,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x200000; op2val:0x9
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TEST_RR_OP(sra, x12, x10, x11, 0x1000, 0x200000, 0x9, x2, 144, x1)
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inst_49:
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// rs1_val == 1048576,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x100000; op2val:0x1
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TEST_RR_OP(sra, x12, x10, x11, 0x80000, 0x100000, 0x1, x2, 148, x1)
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inst_50:
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// rs1_val == 524288, rs2_val == 10
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x80000; op2val:0xa
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TEST_RR_OP(sra, x12, x10, x11, 0x200, 0x80000, 0xa, x2, 152, x1)
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inst_51:
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// rs1_val == 262144,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40000; op2val:0x1f
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TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x40000, 0x1f, x2, 156, x1)
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inst_52:
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// rs1_val == 131072,
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// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20000; op2val:0xb
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x40, 0x20000, 0xb, x2, 160, x1)
|
|
|
|
inst_53:
|
|
// rs1_val == 65536,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10000; op2val:0xa
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x40, 0x10000, 0xa, x2, 164, x1)
|
|
|
|
inst_54:
|
|
// rs1_val == 32768,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8000; op2val:0x10
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x8000, 0x10, x2, 168, x1)
|
|
|
|
inst_55:
|
|
// rs1_val == 8192,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2000; op2val:0xf
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x2000, 0xf, x2, 172, x1)
|
|
|
|
inst_56:
|
|
// rs1_val == 4096,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1000; op2val:0x1d
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x1000, 0x1d, x2, 176, x1)
|
|
|
|
inst_57:
|
|
// rs1_val == 2048,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x800; op2val:0x8
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x8, 0x800, 0x8, x2, 180, x1)
|
|
|
|
inst_58:
|
|
// rs1_val == 1024,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x400; op2val:0x5
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x20, 0x400, 0x5, x2, 184, x1)
|
|
|
|
inst_59:
|
|
// rs1_val == 512,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x200; op2val:0x1b
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x200, 0x1b, x2, 188, x1)
|
|
|
|
inst_60:
|
|
// rs1_val == 256,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x100; op2val:0xd
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x100, 0xd, x2, 192, x1)
|
|
|
|
inst_61:
|
|
// rs1_val == 128,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x80; op2val:0x3
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x10, 0x80, 0x3, x2, 196, x1)
|
|
|
|
inst_62:
|
|
// rs1_val == 64,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40; op2val:0x5
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x2, 0x40, 0x5, x2, 200, x1)
|
|
|
|
inst_63:
|
|
// rs1_val == 32,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20; op2val:0x5
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x1, 0x20, 0x5, x2, 204, x1)
|
|
|
|
inst_64:
|
|
// rs1_val == 16,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10; op2val:0x8
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x10, 0x8, x2, 208, x1)
|
|
|
|
inst_65:
|
|
// rs1_val == 8,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8; op2val:0x3
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x1, 0x8, 0x3, x2, 212, x1)
|
|
|
|
inst_66:
|
|
// rs1_val == 4, rs1_val==4
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4; op2val:0xb
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x4, 0xb, x2, 216, x1)
|
|
|
|
inst_67:
|
|
// rs1_val == 1, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1; op2val:0x8
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x1, 0x8, x2, 220, x1)
|
|
|
|
inst_68:
|
|
// rs1_val==46341,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb505; op2val:0x1e
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0xb505, 0x1e, x2, 224, x1)
|
|
|
|
inst_69:
|
|
// rs1_val==-46339,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0xb503; op2val:0x8
|
|
TEST_RR_OP(sra, x12, x10, x11, -0xb6, -0xb503, 0x8, x2, 228, x1)
|
|
|
|
inst_70:
|
|
// rs1_val==1717986919,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x66666667; op2val:0x10
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x6666, 0x66666667, 0x10, x2, 232, x1)
|
|
|
|
inst_71:
|
|
// rs1_val==858993460,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x33333334; op2val:0xa
|
|
TEST_RR_OP(sra, x12, x10, x11, 0xccccc, 0x33333334, 0xa, x2, 236, x1)
|
|
|
|
inst_72:
|
|
// rs1_val==6,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x6; op2val:0x13
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x6, 0x13, x2, 240, x1)
|
|
|
|
inst_73:
|
|
// rs1_val == 1431655765, rs1_val==1431655765
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x55555555; op2val:0x15
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x2aa, 0x55555555, 0x15, x2, 244, x1)
|
|
|
|
inst_74:
|
|
// rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, rs1_val==0
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x0; op2val:0xa
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x0, 0xa, x2, 248, x1)
|
|
|
|
inst_75:
|
|
// rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x7; op2val:0x7
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x7, 0x7, x2, 252, x1)
|
|
|
|
inst_76:
|
|
// rs1_val==1431655766,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x55555556; op2val:0x13
|
|
TEST_RR_OP(sra, x12, x10, x11, 0xaaa, 0x55555556, 0x13, x2, 256, x1)
|
|
|
|
inst_77:
|
|
// rs1_val==46339,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb503; op2val:0x7
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x16a, 0xb503, 0x7, x2, 260, x1)
|
|
|
|
inst_78:
|
|
// rs1_val==1717986917,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x66666665; op2val:0x1b
|
|
TEST_RR_OP(sra, x12, x10, x11, 0xc, 0x66666665, 0x1b, x2, 264, x1)
|
|
|
|
inst_79:
|
|
// rs1_val==858993458,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x33333332; op2val:0x15
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x199, 0x33333332, 0x15, x2, 268, x1)
|
|
|
|
inst_80:
|
|
// rs1_val==1431655764,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x55555554; op2val:0x7
|
|
TEST_RR_OP(sra, x12, x10, x11, 0xaaaaaa, 0x55555554, 0x7, x2, 272, x1)
|
|
|
|
inst_81:
|
|
// rs1_val==46340,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb504; op2val:0xf
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x1, 0xb504, 0xf, x2, 276, x1)
|
|
|
|
inst_82:
|
|
// rs1_val==-46340,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0xb504; op2val:0x15
|
|
TEST_RR_OP(sra, x12, x10, x11, -0x1, -0xb504, 0x15, x2, 280, x1)
|
|
|
|
inst_83:
|
|
// rs1_val==1717986918,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x66666666; op2val:0x1e
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x1, 0x66666666, 0x1e, x2, 284, x1)
|
|
|
|
inst_84:
|
|
// rs1_val==858993459,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x33333333; op2val:0x1d
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x1, 0x33333333, 0x1d, x2, 288, x1)
|
|
|
|
inst_85:
|
|
// rs1_val==5,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x5; op2val:0x1d
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x5, 0x1d, x2, 292, x1)
|
|
|
|
inst_86:
|
|
// rs2_val == 29, rs1_val==-1431655765
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555; op2val:0x1d
|
|
TEST_RR_OP(sra, x12, x10, x11, -0x3, -0x55555555, 0x1d, x2, 296, x1)
|
|
|
|
inst_87:
|
|
// rs2_val == 30, rs1_val == 16384
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4000; op2val:0x1e
|
|
TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x4000, 0x1e, x2, 300, x1)
|
|
|
|
inst_88:
|
|
// rs1_val == -134217729,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001; op2val:0xb
|
|
TEST_RR_OP(sra, x12, x10, x11, -0x10001, -0x8000001, 0xb, x2, 304, x1)
|
|
|
|
inst_89:
|
|
// rs1_val == -33554433,
|
|
// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001; op2val:0x9
|
|
TEST_RR_OP(sra, x12, x10, x11, -0x10001, -0x2000001, 0x9, x2, 308, x1)
|
|
#endif
|
|
|
|
|
|
RVTEST_CODE_END
|
|
RVMODEL_HALT
|
|
|
|
RVTEST_DATA_BEGIN
|
|
.align 4
|
|
rvtest_data:
|
|
.word 0xbabecafe
|
|
RVTEST_DATA_END
|
|
|
|
RVMODEL_DATA_BEGIN
|
|
|
|
|
|
signature_x3_0:
|
|
.fill 0*(XLEN/32),4,0xdeadbeef
|
|
|
|
|
|
signature_x3_1:
|
|
.fill 7*(XLEN/32),4,0xdeadbeef
|
|
|
|
|
|
signature_x4_0:
|
|
.fill 5*(XLEN/32),4,0xdeadbeef
|
|
|
|
|
|
signature_x2_0:
|
|
.fill 78*(XLEN/32),4,0xdeadbeef
|
|
|
|
#ifdef rvtest_mtrap_routine
|
|
|
|
mtrap_sigptr:
|
|
.fill 64*(XLEN/32),4,0xdeadbeef
|
|
|
|
#endif
|
|
|
|
#ifdef rvtest_gpr_save
|
|
|
|
gpr_save:
|
|
.fill 32*(XLEN/32),4,0xdeadbeef
|
|
|
|
#endif
|
|
|
|
RVMODEL_DATA_END
|