forked from Github_Repos/cvw
147 lines
6.6 KiB
Systemverilog
147 lines
6.6 KiB
Systemverilog
///////////////////////////////////////////
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// ahblite.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: AHB Lite External Bus Unit
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// See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
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// Arbitrates requests from instruction and data streams
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// Connects core to peripherals and I/O pins on SOC
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// Bus width presently matches XLEN
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// Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module ahblite (
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input logic clk, reset,
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// Load control
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input logic UnsignedLoadM,
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input logic [1:0] AtomicMaskedM,
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// Signals from Instruction Cache
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input logic [`PA_BITS-1:0] IFUBusAdr,
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input logic IFUBusRead,
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output logic [`XLEN-1:0] IFUBusHRDATA,
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output logic IFUBusAck,
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// Signals from Data Cache
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input logic [`PA_BITS-1:0] LSUBusAdr,
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input logic LSUBusRead,
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input logic LSUBusWrite,
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input logic [`XLEN-1:0] LSUBusHWDATA,
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output logic [`XLEN-1:0] LSUBusHRDATA,
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input logic [2:0] LSUBusSize,
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output logic LSUBusAck,
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// AHB-Lite external signals
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(* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA,
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(* mark_debug = "true" *) input logic HREADY, HRESP,
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(* mark_debug = "true" *) output logic HCLK, HRESETn,
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(* mark_debug = "true" *) output logic [31:0] HADDR, // *** one day switch to a different bus that supports the full physical address
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(* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA,
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(* mark_debug = "true" *) output logic HWRITE,
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(* mark_debug = "true" *) output logic [2:0] HSIZE,
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(* mark_debug = "true" *) output logic [2:0] HBURST,
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(* mark_debug = "true" *) output logic [3:0] HPROT,
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(* mark_debug = "true" *) output logic [1:0] HTRANS,
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(* mark_debug = "true" *) output logic HMASTLOCK,
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// Delayed signals for writes
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(* mark_debug = "true" *) output logic [2:0] HADDRD,
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(* mark_debug = "true" *) output logic [3:0] HSIZED,
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(* mark_debug = "true" *) output logic HWRITED
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);
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typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
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statetype BusState, NextBusState;
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logic GrantData;
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logic [31:0] AccessAddress;
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logic [2:0] ISize;
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assign HCLK = clk;
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assign HRESETn = ~reset;
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// initially support AHBW = XLEN
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// track bus state
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// Data accesses have priority over instructions. However, if a data access comes
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// while an instruction read is occuring, the instruction read finishes before
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// the data access can take place.
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flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);
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// This case statement computes the desired next state for the AHBlite,
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// prioritizing address translations, then atomics, then data accesses, and
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// finally instructions. This proposition controls HADDR so the PMA and PMP
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// checkers can determine whether the access is allowed. If not, the actual
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// NextWalkerState is set to IDLE.
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// *** This ability to squash accesses must be replicated by any bus
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// interface that might be used in place of the ahblite.
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always_comb
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case (BusState)
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IDLE: if (LSUBusRead) NextBusState = MEMREAD; // Memory has priority over instructions
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else if (LSUBusWrite)NextBusState = MEMWRITE;
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else if (IFUBusRead) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MEMREAD: if (~HREADY) NextBusState = MEMREAD;
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else if (IFUBusRead) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MEMWRITE: if (~HREADY) NextBusState = MEMWRITE;
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else if (IFUBusRead) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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INSTRREAD: if (~HREADY) NextBusState = INSTRREAD;
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else NextBusState = IDLE; // if (IFUBusRead still high)
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default: NextBusState = IDLE;
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endcase
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// bus outputs
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assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
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assign #1 AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0];
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assign #1 HADDR = AccessAddress;
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assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
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assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize;
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assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH
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assign HPROT = 4'b0011; // not used; see Section 3.7
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assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
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assign HMASTLOCK = 0; // no locking supported
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assign HWRITE = NextBusState == MEMWRITE;
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// delay write data by one cycle for
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flop #(`XLEN) wdreg(HCLK, LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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// delay signals for subword writes
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flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD);
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flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
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flop #(1) writereg(HCLK, HWRITE, HWRITED);
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// Route signals to Instruction and Data Caches
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// *** assumes AHBW = XLEN
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assign IFUBusHRDATA = HRDATA;
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assign LSUBusHRDATA = HRDATA;
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assign IFUBusAck = (BusState == INSTRREAD) & (NextBusState != INSTRREAD);
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assign LSUBusAck = (BusState == MEMREAD) & (NextBusState != MEMREAD) | (BusState == MEMWRITE) & (NextBusState != MEMWRITE);
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endmodule
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