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alu.sv
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Renamed RD1D to R1D, etc.
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2021-12-18 21:26:00 -08:00 |
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comparator.sv
|
Renamed zero to eq in flag generation
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2021-12-19 11:49:15 -08:00 |
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controller.sv
|
ALUControl cleanup
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2021-12-19 13:53:45 -08:00 |
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datapath.sv
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Renamed RD1D to R1D, etc.
|
2021-12-18 21:26:00 -08:00 |
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extend.sv
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small synthesis fixes
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2021-05-04 15:21:01 -04:00 |
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forward.sv
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Forwarding logic factoring
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2021-12-18 05:40:38 -08:00 |
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regfile.sv
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Synchronous reset in non-flop blocks
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2021-10-26 08:30:35 -07:00 |
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shifter.sv
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Simplified shifter right input
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2021-12-18 10:25:40 -08:00 |
