Ross Thompson 900939581e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main		2022-04-05 15:42:07 -05:00
..
cache	Changed sram1p1rw to have the same type of bytewrite enables as bram.	2022-03-30 11:38:25 -05:00
ebu	Started make allsynth to try many experiments	2022-02-17 17:57:02 +00:00
fma	Added SystemVerilog flag to fma.do so that fma16 compiles properly	2022-03-31 17:00:38 +00:00
fpu	generating all testfloat vectors	2022-04-04 17:17:12 +00:00
generic	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-04 10:56:10 -05:00
hazard	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
ieu	Moved WriteDataM register into LSU.	2022-03-23 14:17:59 -05:00
ifu	big interrupts refactor	2022-03-30 13:22:41 -07:00
lsu	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-30 11:09:44 -05:00
mmu	Modified clint to support all byte write sizes.	2022-03-31 11:31:52 -05:00
muldiv	Better solution to the integer divider interrupt interaction.	2022-01-12 14:22:18 -06:00
privileged	Fixed bug with CSRRS/CSRRC for MIP/SIP	2022-04-03 20:18:25 +00:00
uncore	Increazed fpga clock speed to 35Mhz.	2022-04-05 15:09:49 -05:00
wally	Added more ILA signals.	2022-04-02 16:39:45 -05:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00