forked from Github_Repos/cvw
249 lines
9.4 KiB
Systemverilog
249 lines
9.4 KiB
Systemverilog
///////////////////////////////////////////
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// clint_apb.sv
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//
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// Written: David_Harris@hmc.edu 14 January 2021
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// Modified:
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//
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// Purpose: Core-Local Interruptor
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// See FE310-G002-Manual-v19p05 for specifications
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//
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// Documentation: RISC-V System on Chip Design Chapter 15
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module clint_apb (
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input logic PCLK, PRESETn,
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input logic PSEL,
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input logic [15:0] PADDR,
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input logic [`XLEN-1:0] PWDATA,
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input logic [`XLEN/8-1:0] PSTRB,
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input logic PWRITE,
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input logic PENABLE,
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output logic [`XLEN-1:0] PRDATA,
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output logic PREADY,
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output logic [63:0] MTIME,
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output logic MTimerInt, MSwInt
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);
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logic MSIP;
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logic [15:0] entry;
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logic memwrite;
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logic [63:0] MTIMECMP;
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integer i, j;
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assign memwrite = PWRITE & PENABLE & PSEL; // only write in access phase
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assign PREADY = 1'b1; // CLINT never takes >1 cycle to respond
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// word aligned reads
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if (`XLEN==64) assign #2 entry = {PADDR[15:3], 3'b000};
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else assign #2 entry = {PADDR[15:2], 2'b00};
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// DH 2/20/21: Eventually allow MTIME to run off a separate clock
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// This will require synchronizing MTIME to the system clock
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// before it is read or compared to MTIMECMP.
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// It will also require synchronizing the write to MTIMECMP.
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// Use req and ack signals synchronized across the clock domains.
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// register access
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if (`XLEN==64) begin:clint // 64-bit
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always @(posedge PCLK) begin
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case(entry)
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16'h0000: PRDATA <= {63'b0, MSIP};
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16'h4000: PRDATA <= MTIMECMP;
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16'hBFF8: PRDATA <= MTIME;
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default: PRDATA <= 0;
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endcase
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end
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always_ff @(posedge PCLK or negedge PRESETn)
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if (~PRESETn) begin
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MSIP <= 0;
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MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts
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end else if (memwrite) begin
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if (entry == 16'h0000) MSIP <= PWDATA[0];
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if (entry == 16'h4000) begin
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for(i=0;i<`XLEN/8;i++)
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if(PSTRB[i])
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MTIMECMP[i*8 +: 8] <= PWDATA[i*8 +: 8]; // ***dh: this notation isn't in book yet - maybe from Ross
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end
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end
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// eventually replace MTIME logic below with timereg
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// timereg tr(PCLK, PRESETn, TIMECLK, memwrite & (entry==16'hBFF8), 1'b0, PWDATA, MTIME, done);
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always_ff @(posedge PCLK or negedge PRESETn)
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if (~PRESETn) begin
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MTIME <= 0;
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end else if (memwrite & entry == 16'hBFF8) begin
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// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
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for(j=0;j<`XLEN/8;j++)
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if(PSTRB[j])
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MTIME[j*8 +: 8] <= PWDATA[j*8 +: 8];
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end else MTIME <= MTIME + 1;
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end else begin:clint // 32-bit
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always @(posedge PCLK) begin
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case(entry)
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16'h0000: PRDATA <= {31'b0, MSIP};
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16'h4000: PRDATA <= MTIMECMP[31:0];
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16'h4004: PRDATA <= MTIMECMP[63:32];
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16'hBFF8: PRDATA <= MTIME[31:0];
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16'hBFFC: PRDATA <= MTIME[63:32];
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default: PRDATA <= 0;
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endcase
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end
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always_ff @(posedge PCLK or negedge PRESETn)
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if (~PRESETn) begin
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MSIP <= 0;
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MTIMECMP <= 0;
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// MTIMECMP is not reset ***?
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end else if (memwrite) begin
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if (entry == 16'h0000) MSIP <= PWDATA[0];
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if (entry == 16'h4000)
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for(j=0;j<`XLEN/8;j++)
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if(PSTRB[j])
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MTIMECMP[j*8 +: 8] <= PWDATA[j*8 +: 8];
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if (entry == 16'h4004)
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for(j=0;j<`XLEN/8;j++)
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if(PSTRB[j])
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MTIMECMP[32 + j*8 +: 8] <= PWDATA[j*8 +: 8];
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// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
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end
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// eventually replace MTIME logic below with timereg
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// timereg tr(PCLK, PRESETn, TIMECLK, memwrite & (entry==16'hBFF8), memwrite & (entry == 16'hBFFC), PWDATA, MTIME, done);
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always_ff @(posedge PCLK or negedge PRESETn)
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if (~PRESETn) begin
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MTIME <= 0;
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// MTIMECMP is not reset
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end else if (memwrite & (entry == 16'hBFF8)) begin
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for(i=0;i<`XLEN/8;i++)
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if(PSTRB[i])
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MTIME[i*8 +: 8] <= PWDATA[i*8 +: 8];
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end else if (memwrite & (entry == 16'hBFFC)) begin
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// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
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for(i=0;i<`XLEN/8;i++)
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if(PSTRB[i])
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MTIME[32 + i*8 +: 8]<= PWDATA[i*8 +: 8];
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end else MTIME <= MTIME + 1;
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end
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// Software interrupt when MSIP is set
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assign MSwInt = MSIP;
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// Timer interrupt when MTIME >= MTIMECMP
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assign MTimerInt = ({1'b0, MTIME} >= {1'b0, MTIMECMP}); // unsigned comparison
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endmodule
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module timeregsync(
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input logic clk, resetn,
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input logic we0, we1,
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input logic [`XLEN-1:0] wd,
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output logic [63:0] q);
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if (`XLEN==64)
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always_ff @(posedge clk or negedge resetn)
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if (~resetn) q <= 0;
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else if (we0) q <= wd;
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else q <= q + 1;
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else
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always_ff @(posedge clk or negedge resetn)
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if (~resetn) q <= 0;
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else if (we0) q[31:0] <= wd;
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else if (we1) q[63:32] <= wd;
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else q <= q + 1;
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endmodule
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module timereg(
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input logic PCLK, PRESETn, TIMECLK,
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input logic we0, we1,
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input logic [`XLEN-1:0] PWDATA,
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output logic [63:0] MTIME,
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output logic done);
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// if (`TIMEBASE_SYNC) begin:timereg // use PCLK for MTIME
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if (1) begin:timereg // use PCLK for MTIME
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timregsync timeregsync(.clk(PCLK), .resetn(PRESETn), .we0, .we1, .wd(PWDATA), .q(MTIME));
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assign done = 1; // immediately completes
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end else begin // use asynchronous TIMECLK
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// TIME counter runs on TIMECLK but bus interface runs on PCLK
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// Need to synchronize reads and writes
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// This is subtle because synchronizing a binary counter on a per-bit basis could give a mix of old and new bits
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// Instead, we use a Gray coded counter that only changes one bit per cycle
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// Synchronizing this for a read is safe because we are guaranteed to get either the old or the new value.
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// Writing to the counter requires a request/acknowledge handshake to ensure the write value is held long enough.
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// The handshake signals are synchronized in each direction across the interface
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// There is no back pressure on instructions, so if multiple counter writes occur ***
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logic req, req_sync, ack, we0_stored, we1_stored, ack_stored, resetn_sync;
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logic [`XLEN-1:0] wd_stored;
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logic [63:0] time_int, time_int_gc, time_gc, MTIME_GC;
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// When a write enable is asserted for a cycle, sample the enables and data and raise a request until it is acknowledged
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// When the acknowledge falls, the transaction is done and the system is ready for another write.
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// ***look at redoing this assuming write enable and data are held rather than pulsed.
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always_ff @(posedge PCLK or negedge PRESETn)
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if (~PRESETn)
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req <= 0; // don't bother resetting wd
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else begin
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req <= we0 | we1 | req & ~ack;
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we0_stored <= we0;
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we1_stored <= we1;
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wd_stored <= PWDATA;
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ack_stored <= ack;
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done <= ack_stored & ~ack;
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end
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// synchronize the reset and reqest into the TIMECLK domain
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sync resetsync(TIMECLK, PRESETn, resetn_sync);
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sync rsync(TIMECLK, req, req_sync);
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// synchronize the acknowledge back to the PCLK domain to indicate the request was handled and can be lowered
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sync async(PCLK, req_sync, ack);
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timeregsync timeregsync(.clk(TIMECLK), .resetn(resetn_sync), .we0(we0_stored), .we1(we1_stored), .wd(wd_stored), .q(time_int));
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binarytogray b2g(time_int, time_int_gc);
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flop gcreg(TIMECLK, time_int_gc, time_gc);
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sync timesync[63:0](PCLK, time_gc, MTIME_GC);
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graytobinary g2b(MTIME_GC, MTIME);
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end
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endmodule
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module binarytogray #(parameter N = `XLEN) (
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input logic [N-1:0] b,
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output logic [N-1:0] g);
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// G[N-1] = B[N-1]; G[i] = B[i] ^ B[i+1] for 0 <= i < N-1
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// requires single layer of N-1 XOR gates
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assign g = b ^ {1'b0, b[N-1:1]};
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endmodule
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module graytobinary #(parameter N = `XLEN) (
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input logic [N-1:0] g,
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output logic [N-1:0] b);
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// B[N-1] = G[N-1]; B[i] = G[i] ^ B[i+1] for 0 <= i < N-1
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// requires rippling through N-1 XOR gates
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genvar i;
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assign b[N-1] = g[N-1];
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for (i=N-2; i >= 0; i--) begin:g2b
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assign b[i] = g[i] ^ b[i+1];
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end
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endmodule
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