README.md

@@ -33,7 +33,7 @@ Then clone the repo, source setup,  make the tests and run regression
 	
 	On the Linux computer where you will be working, log in
 
-Clone your fork of the repo and run the setup script. Change <yourgithubid> to your github id. 
+Clone your fork of the repo and run the setup script.  
 
 	$ cd
 	$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw

addins/riscv-arch-test

@@ -1 +1 @@
-Subproject commit 873d16e748ad60023dcdda3926144957c096e31d
+Subproject commit a3b7f0c2cf89652b8a0cba3146890c512ff8ba44

bin/wally-tool-chain-install.sh

@@ -29,7 +29,7 @@
 
 # Use /opt/riscv for installation - may require running script with sudo
 export RISCV="${1:-/opt/riscv}"
-export PATH=$PATH:$RISCV/bin:/usr/bin
+export PATH=$PATH:$RISCV/bin
 
 set -e # break on error
 
@@ -40,20 +40,20 @@ NUM_THREADS=8  # for >= 32GiB
 #NUM_THREADS=16  # for >= 64GiB
 
 sudo mkdir -p $RISCV
-# *** need to update permissions to local user
 
 # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
-sudo apt update -y
+apt update -y
-sudo apt upgrade -y
+apt upgrade -y
-sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev verilator automake autotools-dev libmpc-dev libmpfr-dev  gperf libtool patchutils bc 
+apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev verilator
+
 # Other python libraries used through the book.
-sudo pip3 install matplotlib scipy scikit-learn adjustText lief
+pip3 install matplotlib scipy scikit-learn adjustText lief
 
 # needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3.
 if ! command -v python &> /dev/null
 then
     echo "WARNING: python3 was installed as python3 rather than python. Creating symlink."
-    sudo ln -sf /usr/bin/python3 /usr/bin/python
+    ln -sf /usr/bin/python3 /usr/bin/python
 fi
 
 # gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain)
@@ -68,12 +68,10 @@ fi
 cd $RISCV
 git clone https://github.com/riscv/riscv-gnu-toolchain
 cd riscv-gnu-toolchain
-#git checkout 2023.01.31 #for 12.2.0; 2023.04.29 for 13.1
+git checkout 2023.01.31 
-# Temporarily use the following commands until gcc-13 is part of riscv-gnu-toolchain (issue #1249)
+./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
-git clone https://github.com/gcc-mirror/gcc -b releases/gcc-13 gcc-13
-./configure --prefix=/opt/riscv --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" --with-gcc-src=`pwd`/gcc-13
-#./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
 make -j ${NUM_THREADS}
+make install
 
 # elf2hex (https://github.com/sifive/elf2hex)
 #The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation. 
@@ -133,9 +131,8 @@ sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
 #pip3 install chardet==3.0.4
 #pip3 install urllib3==1.22
 
-cd $RISCV
 opam init -y --disable-sandboxing
-opam switch create ocaml-base-compiler.4.08.0
+opam switch create ocaml-base-compiler.4.06.1
 opam install sail -y 
 
 eval $(opam config env)
@@ -143,14 +140,13 @@ git clone https://github.com/riscv/sail-riscv.git
 cd sail-riscv
 # Current bug in Sail - use hash that works for Wally
 #   (may remove later if Sail is ever fixed)
-#git checkout 4d05aa1698a0003a4f6f99e1380c743711c32052
+git checkout 4d05aa1698a0003a4f6f99e1380c743711c32052
 make -j ${NUM_THREADS}
 ARCH=RV32 make -j ${NUM_THREADS}
-# next line seems redundant
+ARCH=RV64 make -j ${NUM_THREADS}
-#ARCH=RV64 make -j ${NUM_THREADS}
+ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
-sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
+ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
-sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
 
-sudo pip3 install testresources
+pip3 install testresources
-pip3 install git+https://github.com/riscv/riscof.git
+pip3 install riscof --ignore-installed PyYAML
 

sim/coverage-exclusions-rv64gc.do

@@ -208,12 +208,6 @@ coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item e
 coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item b 1
 coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item s 1
 
-# No irom
-set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"] 
-coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 6
-set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & CacheableF & ~SelIROM"] 
-coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 4
-
 # Excluding reset and clear for impossible case in the wficountreg in privdec
 set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"]
 coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2

tests/coverage/tlbGLB.S

@@ -3,9 +3,8 @@
 //
 // Written: mmendozamanriquez@hmc.edu 4 April 2023
 //          nlimpert@hmc.edu
-// Modified: kevin.j.thomas@okstate.edu May/4/20203
 //
-// Purpose: Coverage for the Page Table Entry Global flag check.
+// Purpose: coverage for the global check. 
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -36,47 +35,43 @@ main:
     li t5, 0x9000000000080080 // try making asid = 0. 
     csrw satp, t5
 
+    # sfence.vma x0, x0
+
     # switch to supervisor mode
-    li a0, 1
+    li a0, 1   
     ecall
 
-    li t5, 0            # j = 0, run nASID only once
+    li t0, 0xC0000000
-    li t3, 32                       //Max amount of Loops = 32
-    li t4, 0x1000                   //offset between addressses.
-    li t1, 0x00008067               //load in jalr x0 x1 0 instruction to be stored
 
-setup:
-    li t0, 0xC0000000               //starting address
     li t2, 0             # i = 0
-    beq t5, zero, loop              //jump to first loop
+    li t5, 0            # j = 0 // now use as a counter for new asid loop 
+    li t3, 32     # Max amount of Loops = 32
 
-loop2:  #jump to each of the addresses in different address space
+loop: bge t2, t3, nASID   # exit loop if i >= loops
-    bge t2, t3, done
+    li t1, 0x00008067 #load in jalr
-    jalr t0                         //jump to instruction at the virtual address
+    sw t1, 0(t0)
-    add t0, t0, t4                  //change address for next loop
+    fence.I
-    addi t2, t2, 1                  //keep track of number of loops ran
+    jalr t0
-    j loop2
+    li t4, 0x1000
-
+    add t0, t0, t4
-loop:   #store jalr across memory
+    addi t2, t2, 1
-    bge t2, t3, nASID   # exit loop if i >= loops
-    sw t1, 0(t0)                    //stores this jalr in the virtual address
-    fence.I                         //invalidate instruction cache
-    jalr t0                         //jump to instruction at the virtual address
-    add t0, t0, t4                  //change address for next loop
-    addi t2, t2, 1                  //keep track of number of loops ran
     j loop
 
-nASID:   #swap to different address space -> jump to each address
+nASID: bne t5, zero, finished
-    li a0, 3                        //swap to machine mode
+    li a0, 3   // go
     ecall
-    li t5, 0x9000100000080080       //swap to address space 1 from 0
+    li t5, 0x9000100000080080 // try making asid = 1 
     csrw satp, t5
-    li a0, 1                        // change back to supervisor mode.
+    li a0, 1   
     ecall
-    li t5, 1                        //flag for finished after loops
+    li t2, 0
-    j setup
+    li t0, 0xC0000000
+    li t5, 1 // make this not zero. 
+    j loop
 
 
+finished:
+    j done
 
 .data
 .align 19