Ross Thompson
fad0366d26
Adding in the ILA to the arty a7.
2023-04-17 14:54:10 -05:00
Ross Thompson
d2272c0620
Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
...
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
Ross Thompson
c9445384d7
Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.
2023-04-14 18:02:16 -05:00
Ross Thompson
b015e736a0
Updated to help debut Jacob's crossbar woes.
2023-04-11 14:22:42 -05:00
Ross Thompson
6123efd5b2
Updates for arty a7.
2023-04-10 17:02:19 -05:00
Ross Thompson
2abd164d03
Fixed syntax errors in arty7 top level.
2023-04-10 16:08:40 -05:00
Ross Thompson
81fb076e9e
Added more support for Arty A7 board.
2023-04-10 16:01:17 -05:00
David Harris
99d179dd3e
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
Ross Thompson
442de3f5b7
Updated fpga constraints.
2023-01-20 20:16:33 -06:00
Ross Thompson
3e1a54e80a
Removed SDC from repo due to copy right issue.
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Modified fpga build flow to reference it outside the repo.
2023-01-20 14:57:06 -06:00
Ross Thompson
1510c2d92f
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 15:38:39 -05:00
Ross Thompson
c88541cf6b
test.
2022-03-28 17:04:58 -05:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
Ross Thompson
a11597b6bd
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
Ross Thompson
af9f97454d
Cleaned up fpga synthesis script.
2021-12-13 18:26:54 -06:00
Ross Thompson
29743c5e9e
Fixed two issues.
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First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
Ross Thompson
c3c9c327b7
Fixed more constraint issues in fpga.
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Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
Ross Thompson
5b4ff4526e
Fixed a bunch of fpga issues.
2021-12-03 17:47:54 -06:00
Ross Thompson
96fb3acefd
Constraints for fpga are still wrong.
2021-12-02 14:23:21 -06:00
Ross Thompson
303324d370
Added tcl commands to build the implementation.
2021-12-02 10:17:30 -06:00
Ross Thompson
e94fb2aaec
Got fpga synthesis running from scripts.
2021-12-01 16:59:04 -06:00
