David Harris
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b4902a6ff9
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First implementation of WFI timeout wait
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2022-04-17 17:20:35 +00:00 |
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David Harris
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6e16922aae
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WFI should set EPC to PC+4
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2022-04-14 17:05:22 +00:00 |
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Ross Thompson
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de868ef3a2
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Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.
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2022-04-07 16:56:28 -05:00 |
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bbracker
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69a0f6e00b
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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bbracker
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4b376e2834
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1st attempt at multiple channel PLIC
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2022-03-24 17:08:10 -07:00 |
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David Harris
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72e83db9fe
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removed csrn and all of its outputs because depricated
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2022-02-15 19:59:29 +00:00 |
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David Harris
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f734afb866
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Just needed to recompile - all good. Now removed uretM because N-mode is depricated
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2022-02-15 19:48:49 +00:00 |
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David Harris
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1326ade1a0
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Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
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2022-02-15 19:20:41 +00:00 |
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Ross Thompson
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862bf2faae
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Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
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2022-01-27 17:11:27 -06:00 |
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Ross Thompson
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4a75e69457
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Merged in the debug ila updates.
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2022-01-18 17:29:21 -06:00 |
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Ross Thompson
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459f4bd3b4
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Hack "fix" to prevent interrupt from occuring during an integer divide.
This is not the desired solution but will allow continued debuging of linux.
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2022-01-12 14:17:16 -06:00 |
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Ross Thompson
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73c488914f
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Added icache access and icache miss to performance counters.
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2022-01-09 22:56:56 -06:00 |
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David Harris
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b36ace221e
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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