3 Commits

Author	SHA1	Message	Date
Ross Thompson	67ff8f27f4	Can now support the following memory and bus configurations. ... 1. dtim/irom only 2. bus only 3. dtim/irom + bus 4. caches + bus	2022-03-11 15:18:56 -06:00
David Harris	da8819d64b	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00