11 Commits

Author	SHA1	Message	Date
Ross Thompson	400b5f7632	Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.	2022-04-04 09:57:26 -05:00
Ross Thompson	51dfa16f59	Updated the fpga test bench.	2022-04-01 17:14:47 -05:00
Ross Thompson	1d7949513d	More cache cleanup.	2022-02-13 15:47:27 -06:00
Ross Thompson	7ffbc6b2ab	Changed names of signals in cache.	2022-02-13 15:06:18 -06:00
David Harris	a6708ed887	cache cleanup	2022-02-03 15:36:11 +00:00
Ross Thompson	2e00186eea	Updated wave.do to match the ifu/lsu changes.	2022-01-28 14:37:15 -06:00
Ross Thompson	862bf2faae	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
David Harris	07425369fc	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
David Harris	6febce0001	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
David Harris	fd13272d4c	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00