Ross Thompson
|
e2cf941a23
|
Possible plic fix?
|
2022-05-22 23:47:01 -05:00 |
|
Ross Thompson
|
c4f1a0362b
|
Fixed receive fifo ITNR bug.
|
2022-05-22 10:55:28 -05:00 |
|
Ross Thompson
|
92a2ad02db
|
Added more debug signals to uart.
|
2022-05-21 19:47:40 -05:00 |
|
David Harris
|
8166fd772e
|
Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
|
2022-05-11 15:08:33 +00:00 |
|
David Harris
|
137b411bea
|
Removed M suffix from interrupts because they are generated asynchronously to pipeline
|
2022-05-11 14:41:55 +00:00 |
|
David Harris
|
9e47fca2b7
|
Changed loop variable in CLINT because of error only seen on VLSI
|
2022-05-03 10:10:28 +00:00 |
|
bbracker
|
9c1e398bb5
|
change how tristate I/O is spoofed in GPIO loopback test
|
2022-04-21 10:31:16 -07:00 |
|
David Harris
|
1e19cf9f14
|
Simplified profile for UART boot; added warnings on UART Rx errors
|
2022-04-21 04:54:45 +00:00 |
|
Kip Macsai-Goren
|
ced763beb6
|
Added GPIO loopback to let outputs cause interrupts
|
2022-04-18 07:22:49 +00:00 |
|
David Harris
|
22842816a8
|
LSU name cleanup
|
2022-04-18 03:18:38 +00:00 |
|
Ross Thompson
|
7135364d1a
|
Increased uart baud rate to 230400.
Added uart signals to debugger.
|
2022-04-17 15:23:39 -05:00 |
|
Ross Thompson
|
22f2e88553
|
UART and clock speed changes to support 30Mhz.
|
2022-04-12 17:56:36 -05:00 |
|
Ross Thompson
|
5faa88acd5
|
Increazed fpga clock speed to 35Mhz.
linux boot is much faster.
|
2022-04-05 15:09:49 -05:00 |
|
Ross Thompson
|
91e99f0d34
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-04-04 10:56:10 -05:00 |
|
Ross Thompson
|
077beb18dd
|
Constraint changes for 40Mhz wally.
|
2022-04-04 10:50:48 -05:00 |
|
Ross Thompson
|
400b5f7632
|
Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
|
2022-04-04 09:57:26 -05:00 |
|
Ross Thompson
|
38160fe6ea
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-04-03 17:56:55 -05:00 |
|
Ross Thompson
|
3db60a1cc1
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-04-02 16:39:54 -05:00 |
|
Ross Thompson
|
35e8c6bb9c
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-04-02 16:35:59 -05:00 |
|
Ross Thompson
|
48c49802b2
|
Fixed linting issues.
|
2022-04-01 15:20:45 -05:00 |
|
Ross Thompson
|
301f20052b
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-04-01 12:50:34 -05:00 |
|
Ross Thompson
|
19a8df9739
|
Added wave config
added new signals to ILA.
|
2022-04-01 12:44:14 -05:00 |
|
bbracker
|
e09079d8b4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-03-31 17:54:43 -07:00 |
|
bbracker
|
55df8bc3f7
|
fix lingering overrun error bug
|
2022-03-31 17:54:32 -07:00 |
|
Ross Thompson
|
48c862d536
|
Added PLIC to ILA.
|
2022-03-31 16:44:49 -05:00 |
|
Ross Thompson
|
da93d14050
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-03-31 16:30:55 -05:00 |
|
Ross Thompson
|
ade4a4cd5e
|
Notes on what to change in ram.sv.
|
2022-03-31 15:48:15 -05:00 |
|
bbracker
|
bdb3417656
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-03-31 13:46:32 -07:00 |
|
bbracker
|
0f7e995055
|
simplify plic logic
|
2022-03-31 13:46:24 -07:00 |
|
Ross Thompson
|
285fc6fd4d
|
Modified clint to support all byte write sizes.
|
2022-03-31 11:31:52 -05:00 |
|
bbracker
|
69a0f6e00b
|
big interrupts refactor
|
2022-03-30 13:22:41 -07:00 |
|
Ross Thompson
|
e4f4e1bd43
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-03-30 11:09:44 -05:00 |
|
Ross Thompson
|
f52ab01362
|
Partial cleanup of memories.
|
2022-03-30 11:09:21 -05:00 |
|
Ross Thompson
|
997c1b87fe
|
rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
|
2022-03-29 23:48:19 -05:00 |
|
Ross Thompson
|
66e9380cfb
|
Partial fix to allow byte write enables with fpga and still get a preload to work.
|
2022-03-29 19:12:29 -05:00 |
|
bbracker
|
d33de3ef6b
|
tabs vs spaces disagreement
|
2022-03-24 17:11:41 -07:00 |
|
bbracker
|
4b376e2834
|
1st attempt at multiple channel PLIC
|
2022-03-24 17:08:10 -07:00 |
|
Ross Thompson
|
86cc758354
|
cleanup of ram.sv
|
2022-03-11 18:09:22 -06:00 |
|
Ross Thompson
|
6d914def08
|
Name cleanup.
|
2022-03-10 18:44:50 -06:00 |
|
Ross Thompson
|
654c4d1148
|
simplified uncore's name for HWDATA.
|
2022-03-10 18:17:44 -06:00 |
|
Ross Thompson
|
1aa87c9f3a
|
Moved subwordwrite to lsu directory.
|
2022-03-10 18:15:25 -06:00 |
|
Ross Thompson
|
d0cf41dbe4
|
Simplified byte write enable logic.
|
2022-03-10 18:13:35 -06:00 |
|
Ross Thompson
|
396c97fc36
|
Byte write enables are passing all configs now.
|
2022-03-10 17:26:32 -06:00 |
|
Ross Thompson
|
d8e71e8e35
|
Progress on the path to getting all configs working with byte write enables.
|
2022-03-10 17:02:52 -06:00 |
|
Ross Thompson
|
67ef46ea92
|
Partially working byte write enables. Works for cache, but not dtim or bus only.
|
2022-03-10 16:11:39 -06:00 |
|
Ross Thompson
|
7a129c75cd
|
Added byte write enables to cache SRAMs.
|
2022-03-10 15:48:31 -06:00 |
|
bbracker
|
2322e66f9f
|
fix lint bugs in PLIC and UART
|
2022-02-22 05:04:18 +00:00 |
|
bbracker
|
c26526c9f3
|
change RX side of UART to aslo be LSB-first
|
2022-02-22 03:34:08 +00:00 |
|
Ross Thompson
|
bd7343b791
|
Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
|
2022-02-16 15:22:19 -06:00 |
|
David Harris
|
de5e80696d
|
Cleaned up synthesis warnings
|
2022-02-11 01:15:16 +00:00 |
|