16 Commits

Author	SHA1	Message	Date
David Harris	da8819d64b	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
Ross Thompson	f4a553fd7d	Fixed testbench so coremark stops.	2022-02-02 11:37:48 -06:00
Ross Thompson	4b4cee3ddd	Added correct stop condition for coremark.	2022-02-02 09:53:51 -06:00
Ross Thompson	5407b72af9	Setup the main regression test to be able to handle coremark.	2022-02-01 17:00:11 -06:00
David Harris	7f91170bab	Comments in LSU code about restructuring	2022-01-27 15:53:59 +00:00
David Harris	07425369fc	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
David Harris	b63e53bbdb	Defined rv32e and rv32emc configs	2022-01-17 14:01:01 +00:00
David Harris	6febce0001	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
David Harris	2bf4676ff8	LSU cleanup	2022-01-14 23:55:27 +00:00
Ross Thompson	aad28366d7	Partial local dtim in lsu configuration.	2022-01-13 17:50:31 -06:00
David Harris	bea6d0856d	Testbench directory cleanup	2022-01-07 17:02:16 +00:00
David Harris	120fb7863f	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	85fa620cfb	Finished removing generate statements	2022-01-05 16:41:17 +00:00
Ross Thompson	06168e67e4	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
David Harris	08e6a10480	Removed imperas mmu tests; using wallypriv instead	2022-01-04 23:14:53 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00