8 Commits

Author	SHA1	Message	Date
Jarred Allen	d99b8f772e	Merge from branch 'main'	2021-04-08 17:19:34 -04:00
Jarred Allen	5afb255251	Begin changes to direct-mapped cache	2021-04-01 13:55:21 -04:00
ushakya22	6b9ae41302	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
Jarred Allen	602271ff7b	rv64i linear control flow now working	2021-03-25 13:02:26 -04:00
Jarred Allen	ebd6b931c6	Fix bug in cache line	2021-03-25 12:59:30 -04:00
Jarred Allen	c1fe16b70b	Give some cache mem inputs a better name	2021-03-24 12:31:50 -04:00
Jarred Allen	a51257abca	Fix compile errors from const not actually being constant (why does Verilog do this)	2021-03-24 00:58:56 -04:00
Jarred Allen	d6ecc3ede0	Begin work on direct-mapped cache	2021-03-23 17:03:02 -04:00