Ross Thompson
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d901f60a6d
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Added flush controls to cachway.
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2021-09-16 16:56:48 -05:00 |
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Ross Thompson
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cae350abb7
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Added invalidate to icache.
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2021-09-16 16:15:54 -05:00 |
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Ross Thompson
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6965bde95c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Refixed some bit width issues in the icache.
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2021-09-09 12:44:02 -05:00 |
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Ross Thompson
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1d370ca71f
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fixed some lint bugs.
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2021-09-09 12:38:57 -05:00 |
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David Harris
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12bd351edf
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Lint cleaning, riscv-arch-test testing
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2021-09-09 11:05:12 -04:00 |
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Ross Thompson
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d6ff89b7e6
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Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits.
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2021-08-26 15:43:02 -05:00 |
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Ross Thompson
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d23b860c96
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Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory.
This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
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2021-08-25 21:09:42 -05:00 |
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Ross Thompson
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c5e2443298
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Replaced dcache generate ORing with or_rows.
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2021-08-25 13:46:36 -05:00 |
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Ross Thompson
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e5336f4ee1
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Rename of DCacheMem to cacheway.
simplified dcache names.
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2021-08-25 13:33:15 -05:00 |
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