David Harris
|
f734afb866
|
Just needed to recompile - all good. Now removed uretM because N-mode is depricated
|
2022-02-15 19:48:49 +00:00 |
|
David Harris
|
1326ade1a0
|
Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
|
2022-02-15 19:20:41 +00:00 |
|
Ross Thompson
|
e2343699d1
|
Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv
|
2022-01-20 16:39:54 -06:00 |
|
Ross Thompson
|
4a75e69457
|
Merged in the debug ila updates.
|
2022-01-18 17:29:21 -06:00 |
|
Ross Thompson
|
a5f773220e
|
Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.
|
2022-01-18 17:19:33 -06:00 |
|
Ross Thompson
|
73c488914f
|
Added icache access and icache miss to performance counters.
|
2022-01-09 22:56:56 -06:00 |
|
David Harris
|
120fb7863f
|
Reformatted MIT license to 95 characters
|
2022-01-07 12:58:40 +00:00 |
|
David Harris
|
b36ace221e
|
Renamed wally-pipelined to pipelined
|
2022-01-04 19:47:41 +00:00 |
|