16 Commits

Author	SHA1	Message	Date
Ross Thompson	de99663b97	Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." ... This reverts commit 70b89e5214.	2022-12-04 00:01:58 +00:00
cturek	70b89e5214	Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.	2022-12-02 21:44:29 +00:00
David Harris	d64cd715f9	Renamed DivStartE to IFDivStartE	2022-12-02 11:30:49 -08:00
David Harris	9c1b7e53e4	FPU divider working with execute stage stall	2022-12-02 11:11:53 -08:00
David Harris	ddba68605e	Renamed DivBusy to FDivBusyE in FPU	2022-11-16 10:13:27 -08:00
cturek	b137a95a35	propagated otfc swap to Rad2 and 4 qslc	2022-11-06 23:32:38 +00:00
cturek	1e927df1a0	Added conditional OTFC swap for simplified int postprocessing	2022-11-06 23:09:09 +00:00
cturek	51fc4de0e1	small signal cleanup	2022-10-26 18:42:49 +00:00
David Harris	dceb6f9034	Moved shift into divsqrt stage and cleaned up comments	2022-10-09 04:45:45 -07:00
David Harris	55e4911cf0	fdivsqrt code cleanup	2022-10-09 03:37:27 -07:00
David Harris	fc4146f409	Adding start signals for integer divider to fdivsqrt	2022-09-29 16:30:25 -07:00
David Harris	cfa83fdd98	For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc	2022-09-21 13:30:35 -07:00
David Harris	811f498f63	renamed q to u for unified digit selection	2022-09-20 04:35:14 -07:00
David Harris	705a2bd97b	Removed D2 and D2b from radix2 stage	2022-09-20 04:20:38 -07:00
David Harris	c77ec2aa9c	Simplified UM initialization	2022-09-20 04:18:12 -07:00
David Harris	8d1408a9d6	Moved fpu modules into subdirectories	2022-09-20 04:12:05 -07:00