11 Commits

Author	SHA1	Message	Date
Ross Thompson	cd0da2e3b3	Updated the names of the *WriteDataM inside the LSU to more meaningful names. ... Moved the FWriteDataMux so that the bus and dtim both get fpu stores. Modified the PMA to disallow double sized reads when XLEN=32.	2022-08-23 10:34:39 -05:00
Ross Thompson	839bede656	Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.	2022-03-30 11:04:15 -05:00
Ross Thompson	ee4b38dce3	dtim writes are supressed on non cacheable operation.	2022-03-12 00:46:11 -06:00
Ross Thompson	9dce2a0679	Towards allowing dtim + bus.	2022-03-11 14:58:21 -06:00
Ross Thompson	6d914def08	Name cleanup.	2022-03-10 18:44:50 -06:00
Ross Thompson	63b1ea88c9	Signal name cleanup.	2022-03-10 18:26:58 -06:00
Ross Thompson	396c97fc36	Byte write enables are passing all configs now.	2022-03-10 17:26:32 -06:00
David Harris	c61cd55c5c	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
Ross Thompson	86bac2a083	partial ifu cleanup.	2022-01-31 16:08:53 -06:00
Ross Thompson	e4ee630a3e	cleanup.	2022-01-31 13:29:04 -06:00
Ross Thompson	9cd502d0af	Encapsulated dtim.	2022-01-31 11:23:55 -06:00