12 Commits

Author	SHA1	Message	Date
Ross Thompson	862bf2faae	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
David Harris	07425369fc	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
David Harris	6febce0001	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
David Harris	fd13272d4c	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
Ross Thompson	85b5dc08a8	Fixed support to allow spills and no icache.	2022-01-12 17:25:16 -06:00
Ross Thompson	786a772444	Improve wavefile by adding performance counters.	2022-01-12 10:53:29 -06:00
Ross Thompson	73c488914f	Added icache access and icache miss to performance counters.	2022-01-09 22:56:56 -06:00
Ross Thompson	04ea93aa27	Added performance counters to wavefile.	2022-01-09 22:42:14 -06:00
Ross Thompson	ae927e2bc6	Fixed wavefile. ... Converted coremark to use elf2hex.	2022-01-09 22:03:10 -06:00
Ross Thompson	75788dd9c2	Changes to wave file.	2022-01-05 14:16:59 -06:00
Ross Thompson	06168e67e4	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00