Commit Graph

7 Commits

Author SHA1 Message Date
Ross Thompson
862bf2faae Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
David Harris
07425369fc Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00
David Harris
6febce0001 Moved Dcache into bus block 2022-01-15 00:39:07 +00:00
David Harris
fd13272d4c Renamed LSUStall to LSUStallM 2022-01-15 00:24:16 +00:00
Ross Thompson
509a0cd3f8 Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
only at the start of a request.  Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm.  On a miss with write back, the inital fetch is handled correctly.  However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.

The solution is to modify how cpu requests are suppressed.  Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
Ross Thompson
75788dd9c2 Changes to wave file. 2022-01-05 14:16:59 -06:00
David Harris
b36ace221e Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00