3 Commits

Author	SHA1	Message	Date
Ross Thompson	955ddcfbe1	Fixed bug in the top level of fpga verilog.	2021-12-03 17:55:36 -06:00
Ross Thompson	e94fb2aaec	Got fpga synthesis running from scripts.	2021-12-01 16:59:04 -06:00
Ross Thompson	5ea9ec0ae6	Created top level FPGA module which replicates the schematic of the initial fpga design.	2021-11-30 17:18:28 -06:00