10 Commits

Author	SHA1	Message	Date
Ross Thompson	51dfa16f59	Updated the fpga test bench.	2022-04-01 17:14:47 -05:00
David Harris	a6708ed887	cache cleanup	2022-02-03 15:36:11 +00:00
David Harris	38bbe23d14	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
David Harris	da8819d64b	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
David Harris	07425369fc	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
David Harris	6febce0001	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
David Harris	120fb7863f	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	85fa620cfb	Finished removing generate statements	2022-01-05 16:41:17 +00:00
Ross Thompson	06168e67e4	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00