7 Commits

Author	SHA1	Message	Date
Ross Thompson	7ca801113e	Added debugging directives to system verilog.	2021-09-27 13:57:46 -05:00
Ross Thompson	80e37d2291	Added SDC defines to each config mode. ... Added sd_top which is the sd card reader.	2021-09-24 12:24:30 -05:00
David Harris	9ae25b0cea	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
Ross Thompson	c749d08542	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
David Harris	e1a1a8395e	Parameterized I$/D$ configurations and added sanity check assertions in testbench	2021-07-20 08:57:13 -04:00
David Harris	4d40b5faef	Added cache configuration to config files	2021-07-19 18:19:46 -04:00
Katherine Parry	c74d26eea4	Fixed lint warning	2021-07-14 21:24:48 -04:00