Jacob Pease
b63927b474
Connected the axi_sdc_controller with an axi crossbar.
...
Added an adrdec.sv to the adrdecs.sv file for the sake of the
cache. Modified Uncore accordingly.
2023-01-13 13:56:01 -06:00
Ross Thompson
1510c2d92f
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 15:38:39 -05:00
Ross Thompson
c88541cf6b
test.
2022-03-28 17:04:58 -05:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
Ross Thompson
a11597b6bd
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
Ross Thompson
af9f97454d
Cleaned up fpga synthesis script.
2021-12-13 18:26:54 -06:00
Ross Thompson
29743c5e9e
Fixed two issues.
...
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
Ross Thompson
c3c9c327b7
Fixed more constraint issues in fpga.
...
Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
Ross Thompson
5b4ff4526e
Fixed a bunch of fpga issues.
2021-12-03 17:47:54 -06:00
Ross Thompson
96fb3acefd
Constraints for fpga are still wrong.
2021-12-02 14:23:21 -06:00
Ross Thompson
303324d370
Added tcl commands to build the implementation.
2021-12-02 10:17:30 -06:00
Ross Thompson
e94fb2aaec
Got fpga synthesis running from scripts.
2021-12-01 16:59:04 -06:00
