17 Commits

Author	SHA1	Message	Date
Ross Thompson	19a93345b5	Reduced icache to 1 port memory.	2021-05-03 14:47:49 -05:00
Ross Thompson	a54c231489	Eliminated extra register and fixed ports to icache. ... Still need to support physical tag check and write in icache memory. Still need to reduce to 1 port SRAM in icache. I would like to refactor the icache code.	2021-05-03 12:04:54 -05:00
Ross Thompson	7b3735fc25	Fixed for the instruction spills.	2021-04-21 16:47:05 -05:00
Ross Thompson	99424fb983	Progress on icache. Fixed some issues aligning the PC with instruction. Still broken.	2021-04-20 21:19:53 -05:00
Jarred Allen	aef57cab50	dcache lints	2021-04-15 21:13:56 -04:00
Jarred Allen	892dfd5a9b	More icache bugfixes	2021-04-14 19:03:33 -04:00
Jarred Allen	c1e2e58ebe	Merge branch 'main' into cache ... Conflicts: wally-pipelined/src/cache/dmapped.sv wally-pipelined/src/cache/line.sv wally-pipelined/src/ifu/icache.sv	2021-04-14 18:24:32 -04:00
Teo Ene	1018a10625	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
Jarred Allen	fc8b8ad7aa	A few more cache fixes	2021-04-13 01:07:40 -04:00
Jarred Allen	d99b8f772e	Merge from branch 'main'	2021-04-08 17:19:34 -04:00
Jarred Allen	5afb255251	Begin changes to direct-mapped cache	2021-04-01 13:55:21 -04:00
ushakya22	6b9ae41302	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
Jarred Allen	602271ff7b	rv64i linear control flow now working	2021-03-25 13:02:26 -04:00
Jarred Allen	ebd6b931c6	Fix bug in cache line	2021-03-25 12:59:30 -04:00
Jarred Allen	c1fe16b70b	Give some cache mem inputs a better name	2021-03-24 12:31:50 -04:00
Jarred Allen	a51257abca	Fix compile errors from const not actually being constant (why does Verilog do this)	2021-03-24 00:58:56 -04:00
Jarred Allen	d6ecc3ede0	Begin work on direct-mapped cache	2021-03-23 17:03:02 -04:00