9 Commits

Author	SHA1	Message	Date
cturek	b3bfdbad18	Added flops for n and m, added B=0 signal	2022-11-13 23:02:43 +00:00
cturek	9c70ab917c	Added A<B signal to fdivsqrt, started postprocessing merge	2022-11-13 22:40:26 +00:00
cturek	333da5c945	Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.	2022-11-06 22:08:18 +00:00
cturek	39bf6a456e	renamed remOp to RemOp	2022-11-03 22:37:25 +00:00
cturek	890b26466f	Added rem/div operation to postprocessor	2022-11-02 17:49:40 +00:00
David Harris	b21e36a788	Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc	2022-09-21 04:55:43 -07:00
David Harris	437fd52bf6	Gated sticky bit in fdiv with SpecialCase	2022-09-20 20:05:00 -07:00
David Harris	811f498f63	renamed q to u for unified digit selection	2022-09-20 04:35:14 -07:00
David Harris	8d1408a9d6	Moved fpu modules into subdirectories	2022-09-20 04:12:05 -07:00