12 Commits

Author	SHA1	Message	Date
James E. Stine	a91c0c8fc7	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
Ross Thompson	570aab4275	Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches.	2021-09-11 15:40:27 -05:00
Katherine Parry	ef28679721	fpu cleanup	2021-07-24 14:59:57 -04:00
Katherine Parry	01f0b4e5df	FDIV and FSQRT work	2021-07-21 14:08:14 -04:00
James E. Stine	12e09a7ace	slight mod to fpdiv - still bug in batch vs. non-batch	2021-07-20 01:47:46 -04:00
Katherine Parry	c9180f4ebd	FDIV and FSQRT passes when simulating in modelsim	2021-07-18 23:00:04 -04:00
Katherine Parry	60dabb9094	fdivsqrt inegrated, but not completley working	2021-07-18 14:03:37 -04:00
Katherine Parry	0acf665a8b	lint is clean	2021-06-07 14:22:54 -04:00
Katherine Parry	75a6097467	fixed lint warnings for fpu and lzd	2021-06-05 12:06:33 -04:00
Katherine Parry	06af239e6c	FMV.D.X imperas test passes	2021-05-20 22:17:59 -04:00
Katherine Parry	db95151d8d	fpu imperas tests run	2021-05-01 02:18:01 +00:00
Katherine Parry	e6a7353847	Added missing files in FPU	2021-04-04 18:09:13 +00:00