59 Commits

Author	SHA1	Message	Date
Ross Thompson	4a75e69457	Merged in the debug ila updates.	2022-01-18 17:29:21 -06:00
Ross Thompson	a5f773220e	Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.	2022-01-18 17:19:33 -06:00
Ross Thompson	e06fb923a1	Better solution to the integer divider interrupt interaction.	2022-01-12 14:22:18 -06:00
Ross Thompson	b294f1fbb0	Oups. My hack for DivE interrupt prevention was wrong.	2022-01-12 14:17:16 -06:00
Ross Thompson	459f4bd3b4	Hack "fix" to prevent interrupt from occuring during an integer divide. ... This is not the desired solution but will allow continued debuging of linux.	2022-01-12 14:17:16 -06:00
Ross Thompson	73c488914f	Added icache access and icache miss to performance counters.	2022-01-09 22:56:56 -06:00
David Harris	120fb7863f	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	c1d6550ccb	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00