6 Commits

Author	SHA1	Message	Date
bbracker	368c94d4ff	working GPIO interrupt demo	2021-04-15 21:09:15 -04:00
bbracker	755e2e5771	merge testbench	2021-04-08 14:28:01 -04:00
bbracker	31c6b2d01f	Yee hoo first draft of PLIC plus self-checking tests	2021-04-04 06:40:53 -04:00
James E. Stine	cff08adc3a	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
ushakya22	6b9ae41302	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
bbracker	85363e941d	AHB bugfixes and sim waveview refactoring	2021-03-18 18:25:12 -04:00