9 Commits

Author	SHA1	Message	Date
Ross Thompson	91fcca9d17	Merged together bram1p1rw with sram1p1rw as sram1p1rw. ... Fixed a major issue with the real SRAM implemenation.	2022-09-21 12:20:00 -05:00
Ross Thompson	b2f4d4aaa7	Added chip enables to sram.	2022-09-20 10:49:14 -05:00
Ross Thompson	2aa5886769	Fixed brom1p1r.sv to have fpga preload.	2022-09-02 15:49:50 -05:00
Ross Thompson	559e093ab5	Fixed up FPGA constraints. ... Added back in the fpga boot rom preload.	2022-09-02 13:54:35 -05:00
David Harris	24ce72f0a2	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 09:52:49 -07:00
Ross Thompson	72b886ec8f	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 09:03:34 -05:00
David Harris	b9dc8d9e33	Cleanup typos	2022-08-25 04:32:19 -07:00
David Harris	fe3147806d	removed simpleram and modified dtim to use bram1p1rw	2022-08-25 03:39:57 -07:00
David Harris	e6077f1f16	Added ROM module and moved memories into generic/mem	2022-08-24 17:03:22 -07:00