Commit Graph

5370 Commits

Author SHA1 Message Date
David Harris
136779563c
Merge pull request #67 from eroom1966/main
Add RVVI Address size to configure MMU operations
2023-02-06 08:01:28 -08:00
eroom1966
3910e90b54 remove dead code for ignoring fflags/fcsr 2023-02-06 15:53:29 +00:00
eroom1966
8705df1136 remove leading space 2023-02-06 14:01:05 +00:00
eroom1966
02b4f9c304 remerge changes 2023-02-06 13:43:12 +00:00
Kevin Kim
95c91e4661 zbb handles sign 2023-02-05 16:50:13 +00:00
Kevin Kim
2edcb9d842 began sign/zero extend 2023-02-05 16:37:32 +00:00
David Harris
71a0479b72
Merge pull request #63 from davidharrishmc/dev
Cleanup
2023-02-04 20:15:12 -08:00
David Harris
ff02bcf49f changed USE_SRAM to modify wally-config rather than wally-shared 2023-02-04 20:13:24 -08:00
David Harris
103781923e Parenthesized reduction operators to avoid DC lint 2023-02-04 18:49:47 -08:00
David Harris
54eafe6b9e Removed redundant USE_SRAM from wally-shared.vh (already in wally-config.vh) 2023-02-04 18:49:25 -08:00
David Harris
7ce4f0da2d Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-04 18:32:31 -08:00
David Harris
5f294f47da
Merge pull request #64 from mmasserfrye/main
Now modifying dtim and irom even when USESRAM=1
2023-02-04 18:11:39 -08:00
Kevin Kim
25d9d52994 modularized byte instruction handling into byte.sv; passes lint 2023-02-05 01:04:39 +00:00
Kevin Kim
b40b1fab52 modularized count into cnt.sv; passes lint 2023-02-05 00:48:26 +00:00
Kevin Kim
0758a272f5 zbb handles popcnt and passes lint 2023-02-05 00:11:24 +00:00
Kevin Kim
5200ed3d2e added population count in generic modules 2023-02-05 00:11:12 +00:00
Madeleine Masser-Frye
31530c85cb Now modifying dtim and irom even when USESRAM=1 2023-02-05 00:02:50 +00:00
Kevin Kim
049f2e1e87 Started count instructions 2023-02-04 20:01:41 +00:00
David Harris
683c5b79c6 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-04 09:59:44 -08:00
David Harris
aba8b9a64b More progress on debug.S, but it crashes in Spike 2023-02-04 09:59:22 -08:00
Ross Thompson
9c5c041122 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-04 11:28:26 -06:00
Ross Thompson
9b7a35e848 Updates to imperas test bench. 2023-02-04 11:28:23 -06:00
David Harris
1bb5599806 Developing debug test 2023-02-04 08:31:47 -08:00
David Harris
8e9183962d Fixed license on testbench files 2023-02-04 08:19:20 -08:00
David Harris
0f7ea52f9b Started making debug testcase 2023-02-04 08:18:55 -08:00
David Harris
88ef0503fd Renamed wally-piplined.do to wally.do 2023-02-04 04:38:41 -08:00
David Harris
20a03808a1
Merge pull request #62 from davidharrishmc/dev
../synthDC/Makefile
2023-02-04 04:29:56 -08:00
David Harris
3f22b62601 Added license headers 2023-02-04 04:29:27 -08:00
David Harris
6b3d056713 ../synthDC/Makefile 2023-02-04 04:19:09 -08:00
David Harris
e2061abda9
Merge pull request #53 from davidharrishmc/dev
Removed pipelined hierarchy and renamed regression to sim
2023-02-04 04:15:02 -08:00
David Harris
b13087e706 Fixed merge issues on synthDC PR 2023-02-04 04:13:40 -08:00
David Harris
e0915acad9 Improved illegal NaN-box detection and formatted fsgninj 2023-02-04 03:42:20 -08:00
David Harris
363b7f56a5
Merge pull request #61 from mmasserfrye/main
USE_SRAM parameter, makefile config cleaning
2023-02-04 03:28:44 -08:00
Madeleine Masser-Frye
7b0da71297 finishing the job of the last commit 2023-02-04 10:24:01 +00:00
Madeleine Masser-Frye
d9e1323e57 added use sram parameter, cleaned up config writing, added single synth functionality to wallySynth 2023-02-04 09:50:36 +00:00
David Harris
d4a7679926
Merge pull request #60 from ross144/main
Optimized PCLink logic.
2023-02-03 16:42:27 -08:00
Ross Thompson
c4a9354c13 Replaced PCLinkX registers with a +2/4 adder in the execution stage.
David and I estimate this is lower hardware cost.
2023-02-03 18:19:47 -06:00
Ross Thompson
6dcce8389a Change CurrPtr to Ptr in RAS. 2023-02-03 17:40:20 -06:00
Kevin Kim
c694bde104 Merge branch 'main' of https://github.com/kipmacsaigoren/cvw 2023-02-03 18:39:26 +00:00
Kevin Kim
8c9107ffa4 arch32ba includes the 32i_m tests instead of 64 2023-02-03 17:40:02 +00:00
Kip Macsai-Goren
1096a4e2a5 Merge remote-tracking branch 'upstream/main' into main 2023-02-03 09:31:06 -08:00
David Harris
ed02d5a077 Removed redundant line from synthesis makefile 2023-02-03 08:36:51 -08:00
David Harris
d7ae05ae8e Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-03 08:36:11 -08:00
David Harris
398992db3b Updated division radix test script with paths, but script is out of date for files it manipulates 2023-02-03 08:36:03 -08:00
Kevin Kim
c7ce9242cb Merge branch 'main' of https://github.com/kipmacsaigoren/cvw 2023-02-03 16:00:36 +00:00
Kevin Kim
ac9e672e3e ALU changes (ZBB)
- handles inverted operand instructions
- handles shift-and-add instructions
2023-02-03 16:00:32 +00:00
David Harris
02bdaf858c
Merge pull request #54 from ross144/main
Fixed issue #50, itlb and dcache flush interlock
2023-02-03 06:30:30 -08:00
Ross Thompson
370931c1cd Fixed bug #49.
FFLAGS was updated while the pipeline was stalled.
Also I found serveral performance counters which had similar issues.
2023-02-03 00:39:26 -06:00
Ross Thompson
a4907b5d29 Lee Moore found another bug using imperas.
An ITLB miss concurrent with a d cache flush did not interlock.
The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
2023-02-02 23:52:21 -06:00
Kevin Kim
cb6e80a62b
Merge branch 'openhwgroup:main' into main 2023-02-02 21:41:55 -08:00