13 Commits

Author	SHA1	Message	Date
David Harris	35d0a951d2	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
Katherine Parry	921debf930	removed underflow from inexactct calculation	2022-07-18 17:51:18 +00:00
Katherine Parry	e251022269	merged floating-point radix-2 divider with radix-4	2022-07-15 20:16:59 +00:00
David Harris	dd4fa7c682	qslc_r4a2 generator	2022-06-09 17:26:47 +00:00
Katherine Parry	8fa0fc4229	fma synth warnings and errors removed	2022-06-06 16:06:04 +00:00
Katherine Parry	6b39b8c702	fixed compilation errors	2022-06-03 15:34:17 +00:00
Katherine Parry	f35450207f	single and double conversions pass all tests	2022-05-25 23:02:02 +00:00
Katherine Parry	5d34db85b2	Fixed unpacker bug LT EQ LE pass testfloat	2022-05-20 17:19:50 +00:00
David Harris	72bc64ef28	Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.	2022-02-05 04:16:18 +00:00
David Harris	38bbe23d14	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
David Harris	325724f556	LSU Cleanup	2022-01-15 01:11:17 +00:00
Katherine Parry	b3ebce0365	some FPU test fixes	2022-01-06 23:03:20 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00