Noah Boorstin
e7fae21eb8
busybear: add COUNTERS define
2021-03-16 21:08:47 -04:00
Ross Thompson
4c8952de6a
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
2021-03-15 12:39:44 -05:00
Thomas Fleming
1294235837
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-03-11 00:15:58 -05:00
Ross Thompson
87ed6d510c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-05 15:27:22 -06:00
Ross Thompson
301166d062
Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
2021-03-05 15:23:53 -06:00
Thomas Fleming
be6ee84d87
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 15:46:51 -05:00
Thomas Fleming
8c97143be6
Place tlb parameters into constant header file
2021-03-05 13:35:24 -05:00
Noah Boorstin
f48af209c4
busybear: make CSRs only weird for us
2021-03-05 00:46:32 +00:00
Noah Boorstin
26d4024b33
busybear: fix bootram range
2021-03-01 17:45:21 +00:00
Noah Boorstin
6e70ae8b3d
busybear: add 2nd dtim for bootram
2021-02-28 16:08:54 +00:00
Noah Boorstin
edd5e9106d
busybear: remove gpio, start adding 2nd ram
2021-02-28 06:02:40 +00:00
Noah Boorstin
4358f086be
update busybear testbench to conform to new structure
...
aaaaaaaaaaaaaaaaaahhhh so many changes
also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
2021-01-30 19:19:00 +00:00
Noah Boorstin
194d5b55ab
update busybear testbench to conform to new structure
2021-01-29 17:46:50 +00:00
Noah Boorstin
dabb026104
busybear: lie about MISA to match OVP's MISA
2021-01-29 00:58:56 -05:00
Noah Boorstin
6c567aab9a
Update busybear tests to conform to new directory structure
2021-01-25 20:37:18 -05:00
David Harris
fa18052348
Added test configurations
2021-01-25 11:28:43 -05:00
