15 Commits

Author	SHA1	Message	Date
Ross Thompson	7289fa8d44	Reduced complexity of spill logic by ensuring the irom outputs offset instrutions on a spill.	2023-01-18 19:10:34 -06:00
Ross Thompson	026d09b79b	More IROM cleanup.	2023-01-18 18:47:02 -06:00
Ross Thompson	19e4d0f7cd	Cleanup dtim and irom.	2023-01-18 18:44:30 -06:00
David Harris	8c6ddcc15b	changed name to CORE-V-WALLY	2023-01-11 15:15:08 -08:00
David Harris	3ea4dd4898	Changed Wally to CORE-V Wally	2023-01-11 14:03:44 -08:00
David Harris	739c2c8322	Changed MIT license to Solderpad License	2023-01-10 11:35:20 -08:00
David Harris	01525399cc	Removed unused signals; added check for atomic in pmachecker	2023-01-07 05:59:56 -08:00
Ross Thompson	a5c15fd801	Fixed first problem with the rv64i IROM.	2022-10-11 11:35:40 -05:00
David Harris	e4c5754b3a	Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width	2022-10-10 09:10:55 -07:00
Ross Thompson	427db1f55f	Renamed brom1p1r to rom1p1r. ... removed used file bram2p1r1w.sv.	2022-09-21 12:31:20 -05:00
Ross Thompson	b2f4d4aaa7	Added chip enables to sram.	2022-09-20 10:49:14 -05:00
David Harris	921a49921b	Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM	2022-08-26 21:05:20 -07:00
David Harris	f782fe9367	Fixed brom name	2022-08-25 12:48:00 -07:00
David Harris	78618f5fc0	Renaming LSU signals from busdp	2022-08-25 11:05:10 -07:00
David Harris	5dc4fb757a	Continued busdp/ebu simplification	2022-08-25 10:20:02 -07:00