54 Commits

Author	SHA1	Message	Date
Ross Thompson	49eea2add5	Fixed bug with flush dirty not cleared in the correct cache line.	2022-01-05 14:14:01 -06:00
David Harris	f04856ee94	Removed more generate statements	2022-01-05 16:01:03 +00:00
Ross Thompson	f89c1d91dc	Renamed most signals inside cache.sv so they are agnostic to i or d.	2022-01-04 23:52:42 -06:00
Ross Thompson	9eda7c12bd	the i and d caches now share common verilog.	2022-01-04 23:40:37 -06:00