David Harris
|
6a555032eb
|
simpleram clk and reset simplification
|
2022-01-25 17:34:15 +00:00 |
|
Ross Thompson
|
9982549057
|
Changed the IROM and DTIM memories to behave like edge-triggered srams.
|
2022-01-21 15:42:54 -06:00 |
|
David Harris
|
07425369fc
|
Renamed wallypipelinedhart to wallypipelinedcore
|
2022-01-20 16:02:08 +00:00 |
|
Ross Thompson
|
a973681a90
|
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
|
2022-01-13 22:21:43 -06:00 |
|