11 Commits

Author	SHA1	Message	Date
Katherine Parry	8420b1e87c	removed some debuging code accedentally pushed	2022-06-02 22:45:19 +00:00
Katherine Parry	03280c0f9c	added createallvectors	2022-06-02 21:56:05 +00:00
Katherine Parry	9a09ee3a35	fpu paramaterized - except fdivsqrt	2022-06-02 19:50:28 +00:00
Katherine Parry	c3d07b2c46	generating all testfloat vectors	2022-04-04 17:17:12 +00:00
Ross Thompson	33b9b5423d	reverted temporary change to configs.	2022-03-22 22:31:34 -05:00
Ross Thompson	c233ef9768	Reverted change to configuration which caused issue with lint.	2022-03-22 21:44:08 -05:00
Katherine Parry	e3d01c875b	FMA parameterized and FMA testbench reworked	2022-03-19 19:39:03 +00:00
Ross Thompson	67ff8f27f4	Can now support the following memory and bus configurations. ... 1. dtim/irom only 2. bus only 3. dtim/irom + bus 4. caches + bus	2022-03-11 15:18:56 -06:00
David Harris	da8819d64b	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
David Harris	b63e53bbdb	Defined rv32e and rv32emc configs	2022-01-17 14:01:01 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00