Ross Thompson
6e803b724e
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Shreya Sanghai
0369fc5d1e
Cherry Pick merge of Shreya's localhistory predictor changes into main.
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fixed minor bugs in localHistory
2021-04-15 09:04:36 -05:00
Ross Thompson
98a04abe6c
Merge remote-tracking branch 'refs/remotes/origin/tests' into tests
2021-04-06 21:20:55 -05:00
Shreya Sanghai
df149d1be7
fixed minor bugs in localHistory
2021-04-01 13:40:08 -04:00
Ross Thompson
9172e52286
Corrected a number of bugs in the branch predictor.
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Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
2021-03-31 11:54:02 -05:00
Ross Thompson
2a308309e4
fixed some bugs with the RAS.
2021-03-30 13:57:40 -05:00
Ross Thompson
84ad1353e4
Fixed a bunch of bugs with the RAS.
2021-03-23 21:49:16 -05:00
Ross Thompson
49348d734b
fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle.
2021-03-23 20:06:45 -05:00
Ross Thompson
95dbc5f1fa
fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled.
2021-03-23 16:53:48 -05:00
Ross Thompson
1091dd10c1
Switched to gshare from global history.
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Fixed a few minor bugs.
2021-03-18 16:05:59 -05:00
Shreya Sanghai
36f0631203
added gshare and global history predictor
2021-03-16 17:03:01 -04:00
Shreya Sanghai
9eed875886
added global history branch predictor
2021-03-16 16:06:40 -04:00
Ross Thompson
7743d8edc3
Cleanup of the branch predictor flush and stall controls.
2021-03-12 14:57:53 -06:00
Ross Thompson
52d95d415f
Converted to using the BTB to predict the instruction class.
2021-03-04 09:23:35 -06:00
Ross Thompson
7592a0dacb
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
Ross Thompson
9b3637bd87
RAS needs to be reset or preloaded. For now I just reset it.
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Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
00de91cc87
Added FlushF to hazard unit.
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Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
c6ebe7733b
Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
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About 149307ns of simulation run.
2021-02-18 21:32:15 -06:00
Ross Thompson
5df7e959f3
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
Ross Thompson
78db3654c6
We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.
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This is not yet tested but the system verilog does compile.
2021-02-15 14:51:39 -06:00
Ross Thompson
3ec1f668fc
added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior.
2021-02-14 15:13:55 -06:00
Ross Thompson
30df1cdd25
The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables.
2021-02-14 11:06:31 -06:00
