11 Commits

Author	SHA1	Message	Date
Ross Thompson	96fb3acefd	Constraints for fpga are still wrong.	2021-12-02 14:23:21 -06:00
Ross Thompson	303324d370	Added tcl commands to build the implementation.	2021-12-02 10:17:30 -06:00
Ross Thompson	0d47749cb5	Separated timing constraints from ILA.	2021-12-01 18:15:04 -06:00
Ross Thompson	e94fb2aaec	Got fpga synthesis running from scripts.	2021-12-01 16:59:04 -06:00
Ross Thompson	5ea9ec0ae6	Created top level FPGA module which replicates the schematic of the initial fpga design.	2021-11-30 17:18:28 -06:00
Ross Thompson	d5f445e0fd	Added make clean to fpga IP generator.	2021-11-29 18:42:28 -06:00
Ross Thompson	a528a86607	Created Makefile to manage IP generation.	2021-11-29 18:33:58 -06:00
Ross Thompson	51807379a8	Added final IP generator script (proc_sys_reset).	2021-11-29 17:43:47 -06:00
Ross Thompson	8aa87958a9	Added ddr4 generator script.	2021-11-29 15:56:57 -06:00
Ross Thompson	da4ed957aa	Created tcl scripts to build 2 of the 4 xilinx IP.	2021-11-29 11:26:08 -06:00
Ross Thompson	9150133c7d	Fpga simualtion files.	2021-10-11 10:24:40 -05:00