14 Commits

Author	SHA1	Message	Date
Ross Thompson	4c8952de6a	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
Thomas Fleming	1294235837	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/ebu/ahblite.sv	2021-03-11 00:15:58 -05:00
David Harris	17c0f9629a	WALLY-LRSC atomic test passing	2021-03-09 09:28:25 -05:00
Ross Thompson	301166d062	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
Thomas Fleming	8c97143be6	Place tlb parameters into constant header file	2021-03-05 13:35:24 -05:00
David Harris	d00d42cf9a	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	8dec69c2ce	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	a357f2a0e7	Connected AHB bus to Uncore	2021-01-29 23:43:48 -05:00
David Harris	9a51bb27c3	Implemented adrdec for uncore	2021-01-29 17:28:53 -05:00
David Harris	ed3cb83c10	Added ahblite bus interface unit	2021-01-29 01:07:17 -05:00
David Harris	b88508ca11	Repartitioned datapath and controller into ieu	2021-01-27 06:40:26 -05:00
David Harris	1d9c741c00	Reset Vector moved to config file	2021-01-25 15:57:36 -05:00
David Harris	fa18052348	Added test configurations	2021-01-25 11:28:43 -05:00