69 Commits

Author	SHA1	Message	Date
David Harris	72bc64ef28	Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.	2022-02-05 04:16:18 +00:00
David Harris	fb041fe06a	rv32e	2022-02-04 01:56:30 +00:00
David Harris	ef5af9b5fd	renamed configs	2022-02-03 23:36:41 +00:00
David Harris	38bbe23d14	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
David Harris	da8819d64b	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
David Harris	68a6b4af3d	Removed Busybear and Buildroot Configuration	2022-02-02 20:32:22 +00:00
David Harris	4ba37d5cc0	Config file & wally-riscv-arch-test cleanup	2022-02-02 16:35:52 +00:00
David Harris	090533cfe9	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
David Harris	448acedd8b	Set up rv32emc config	2022-01-27 14:37:58 +00:00
David Harris	748375c82f	Updated configs to fix GPIO address to match FU540	2022-01-26 18:16:34 +00:00
David Harris	b63e53bbdb	Defined rv32e and rv32emc configs	2022-01-17 14:01:01 +00:00
Ross Thompson	3bec276862	Added tim only test to regression-wally. Minor cleanup to ifu.	2022-01-14 11:13:06 -06:00
Ross Thompson	a973681a90	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00
Ross Thompson	aad28366d7	Partial local dtim in lsu configuration.	2022-01-13 17:50:31 -06:00
Ross Thompson	960af4b70f	Set rv32ic to not use icache.	2022-01-12 14:10:09 -06:00
David Harris	401a5b1779	Removed unused coremark_bare	2022-01-10 05:05:55 +00:00
David Harris	39d5570d2c	Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.	2022-01-10 05:04:13 +00:00
Ross Thompson	06168e67e4	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00