Shreya Sanghai
9eed875886
added global history branch predictor
2021-03-16 16:06:40 -04:00
Shreya Sanghai
74f1641c5a
Merge branch 'counters' into main
...
added a configurable number of performance counters
2021-03-16 11:01:30 -04:00
Ross Thompson
4c8952de6a
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
2021-03-15 12:39:44 -05:00
Thomas Fleming
1294235837
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-03-11 00:15:58 -05:00
David Harris
17c0f9629a
WALLY-LRSC atomic test passing
2021-03-09 09:28:25 -05:00
Ross Thompson
87ed6d510c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-05 15:27:22 -06:00
Ross Thompson
301166d062
Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
2021-03-05 15:23:53 -06:00
Thomas Fleming
be6ee84d87
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 15:46:51 -05:00
Thomas Fleming
8c97143be6
Place tlb parameters into constant header file
2021-03-05 13:35:24 -05:00
Noah Boorstin
f48af209c4
busybear: make CSRs only weird for us
2021-03-05 00:46:32 +00:00
Shreya Sanghai
f0ec365117
added performance counters
2021-03-04 11:42:52 -05:00
Teo Ene
396dc61564
Linux CoreMark and baremetal CoreMark split into two separate tests/configs
2021-03-04 07:44:33 -06:00
Teo Ene
6ebb79abe0
Linux CoreMark is operational
2021-03-04 05:58:18 -06:00
Teo Ene
08a7f6ec25
In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches
2021-03-04 01:27:05 -06:00
Noah Boorstin
26d4024b33
busybear: fix bootram range
2021-03-01 17:45:21 +00:00
Noah Boorstin
6e70ae8b3d
busybear: add 2nd dtim for bootram
2021-02-28 16:08:54 +00:00
Noah Boorstin
edd5e9106d
busybear: remove gpio, start adding 2nd ram
2021-02-28 06:02:40 +00:00
Teo Ene
61b872a3e8
Changed TIMBASE in coremark config file
2021-02-25 11:03:41 -06:00
David Harris
d00d42cf9a
Merged bus into main
2021-02-25 00:28:41 -05:00
Teo Ene
3e5de35fc4
Added provisional coremark files from work with Elizabeth
2021-02-24 20:07:07 -06:00
David Harris
8dec69c2ce
Added MUL
2021-02-15 22:27:35 -05:00
David Harris
3551cc859b
Data memory bus integration
2021-02-07 23:21:55 -05:00
Brett Mathis
79cb7ed571
Parallel FSR's and F CTRL logic
2021-02-04 02:25:55 -06:00
Noah Boorstin
4358f086be
update busybear testbench to conform to new structure
...
aaaaaaaaaaaaaaaaaahhhh so many changes
also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
2021-01-30 19:19:00 +00:00
David Harris
a357f2a0e7
Connected AHB bus to Uncore
2021-01-29 23:43:48 -05:00
David Harris
9a51bb27c3
Implemented adrdec for uncore
2021-01-29 17:28:53 -05:00
Teo Ene
3d02d6f09f
Added AHBW to rv32ic config file as well
2021-01-29 12:29:08 -06:00
Noah Boorstin
194d5b55ab
update busybear testbench to conform to new structure
2021-01-29 17:46:50 +00:00
David Harris
a94c09cad8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 01:07:22 -05:00
David Harris
ed3cb83c10
Added ahblite bus interface unit
2021-01-29 01:07:17 -05:00
Noah Boorstin
dabb026104
busybear: lie about MISA to match OVP's MISA
2021-01-29 00:58:56 -05:00
David Harris
b88508ca11
Repartitioned datapath and controller into ieu
2021-01-27 06:40:26 -05:00
Noah Boorstin
6c567aab9a
Update busybear tests to conform to new directory structure
2021-01-25 20:37:18 -05:00
David Harris
1d9c741c00
Reset Vector moved to config file
2021-01-25 15:57:36 -05:00
David Harris
fa18052348
Added test configurations
2021-01-25 11:28:43 -05:00
