Kip Macsai-Goren
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94f03b0d78
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unnecessary comments cleanup
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2023-03-29 19:32:57 -07:00 |
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Kip Macsai-Goren
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da905b4eb9
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Resolved ImperasDV receiving incorrect cause values
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2023-03-29 15:04:56 -07:00 |
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David Harris
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de2a0da9e9
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Reduced number of bits in mcause and medeleg registers
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2023-03-29 07:02:09 -07:00 |
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David Harris
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20ebf7e536
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CSRS privileged coverage test
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2023-03-28 04:37:56 -07:00 |
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Ross Thompson
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730f3ac84e
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Fixed all tap/space issue in RTL.
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2023-03-24 17:32:25 -05:00 |
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David Harris
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99c471ccfe
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Added csrwrites.S test case for privileged tests
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2023-03-23 10:55:32 -07:00 |
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David Harris
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32c54db595
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Fix Issue #142: SCOUNTEREN powers up at 1 instead of 0
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2023-03-22 04:41:57 -07:00 |
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David Harris
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031cc6967a
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Fix Issue #120 about SIE/SIP being 0 unless MIDELEG bits are set. However, this fix breaks the wally32/64priv tests in regression.
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2023-03-18 10:10:58 -07:00 |
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Kip Macsai-Goren
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0ba1a59a70
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added reset values to stime and stimecmp registers
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2023-03-04 15:06:15 -08:00 |
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David Harris
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d50658addf
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Fixed missing assign when SSTC is not supported
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2023-02-26 07:12:13 -08:00 |
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David Harris
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27acb90217
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Fixed SSTC being unusable in M-MODE without Status.TM. Disable STIMECMP registers when SSTC_SUPPORTED = 0
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2023-02-26 06:30:43 -08:00 |
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David Harris
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d83c61cafc
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Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass.
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2023-02-16 07:37:12 -08:00 |
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David Harris
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99d179dd3e
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Removed pipelined level of hierarchy
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2023-02-02 14:14:11 -08:00 |
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