13 Commits

Author	SHA1	Message	Date
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
Noah Boorstin	4358f086be	update busybear testbench to conform to new structure ... aaaaaaaaaaaaaaaaaahhhh so many changes also the testbench now uses another internal signal, which I don't like, but I can't think of a better option rn	2021-01-30 19:19:00 +00:00
David Harris	a357f2a0e7	Connected AHB bus to Uncore	2021-01-29 23:43:48 -05:00
David Harris	9a51bb27c3	Implemented adrdec for uncore	2021-01-29 17:28:53 -05:00
Teo Ene	3d02d6f09f	Added AHBW to rv32ic config file as well	2021-01-29 12:29:08 -06:00
Noah Boorstin	194d5b55ab	update busybear testbench to conform to new structure	2021-01-29 17:46:50 +00:00
David Harris	a94c09cad8	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-01-29 01:07:22 -05:00
David Harris	ed3cb83c10	Added ahblite bus interface unit	2021-01-29 01:07:17 -05:00
Noah Boorstin	dabb026104	busybear: lie about MISA to match OVP's MISA	2021-01-29 00:58:56 -05:00
David Harris	b88508ca11	Repartitioned datapath and controller into ieu	2021-01-27 06:40:26 -05:00
Noah Boorstin	6c567aab9a	Update busybear tests to conform to new directory structure	2021-01-25 20:37:18 -05:00
David Harris	1d9c741c00	Reset Vector moved to config file	2021-01-25 15:57:36 -05:00
David Harris	fa18052348	Added test configurations	2021-01-25 11:28:43 -05:00