Commit Graph

14 Commits

Author SHA1 Message Date
David Harris
329fea9329 Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath 2022-02-28 20:50:51 +00:00
ushakya22
5f916d17d2 Moved order of reading a, b, and result from test vectors file so that result
matches up with inputs a and b
2022-02-21 17:28:11 +00:00
ushakya22
3abc2c0592 - created new testbench file instead of having it at the bottom of the srt file
- uses unpacker to parse 64 bit floating point numbers
- updated testbench to read from new testvectors generated by exptestbench

Notes:
MEM_WIDTH updated to be 64*3
Input numbers and output result is 64 bit number
MEM_SIZE set to 60000
2022-02-21 16:24:50 +00:00
ushakya22
1ea3e8120a - Created exponent divsion module
- top module includes exponent module now

Notes:
- may be a better implementation of the exponent module rather than
having what I believe are two adders currently
2022-02-21 16:13:30 +00:00
ushakya22
3d5b407755 Changed Makefile to compile exptestgen instead of testgen 2022-02-21 16:08:45 +00:00
ushakya22
ec3fa45f86 reverted srt_standford back to original file pre modifications by Udeema 2022-02-21 16:08:09 +00:00
ushakya22
ed452aff5f verilator lint for srt 2022-02-21 16:05:43 +00:00
ushakya22
a3a572fe5f Created test vector generation file for exponent and mantissa division 2022-02-21 16:04:41 +00:00
David Harris
dee2822359 srt fixes 2022-02-14 18:40:27 +00:00
David Harris
99aacd5aca srt batch files 2022-02-14 18:37:46 +00:00
ushakya22
4170b54c28 work in progress exponent handling 2022-02-14 18:24:29 +00:00
ushakya22
f87667d120 Added unpacker into testbench for srt 2022-02-12 22:05:18 +00:00
David Harris
7d13740a11 Mixed C and assembly language test cases; SRT initial version passing tests 2022-01-13 21:45:54 +00:00
David Harris
b36ace221e Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00