7 Commits

Author	SHA1	Message	Date
Ross Thompson	78ab9f59af	Updated GPIO signal names to reflect book.	2023-03-24 18:55:43 -05:00
Ross Thompson	55335d1db6	Updated top level fpga file.	2022-11-18 11:10:45 -06:00
Ross Thompson	6250a65ede	added new constraints for fpga.	2022-09-17 22:20:06 -05:00
Ross Thompson	29743c5e9e	Fixed two issues. ... First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly. Second the bidir buffer for the sd card was connected backwards.	2021-12-07 12:15:50 -06:00
Ross Thompson	955ddcfbe1	Fixed bug in the top level of fpga verilog.	2021-12-03 17:55:36 -06:00
Ross Thompson	e94fb2aaec	Got fpga synthesis running from scripts.	2021-12-01 16:59:04 -06:00
Ross Thompson	5ea9ec0ae6	Created top level FPGA module which replicates the schematic of the initial fpga design.	2021-11-30 17:18:28 -06:00