4 Commits

Author	SHA1	Message	Date
David Harris	2e2aa2a972	connected signals in tlb by name instead of .*	2021-07-06 17:22:10 -04:00
David Harris	032c38b7e7	MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB	2021-07-06 15:29:42 -04:00
David Harris	d58cad89a8	Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines	2021-07-06 10:38:30 -04:00
David Harris	694badcc6b	Created tlbcontrol module to hide details	2021-07-06 03:25:11 -04:00