Ross Thompson
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a445bedcd2
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Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
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2021-12-19 14:57:42 -06:00 |
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Ross Thompson
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225cd5a114
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Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
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2021-12-19 14:00:30 -06:00 |
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Ross Thompson
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cd3c1032b7
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Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states.
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2021-12-19 13:55:57 -06:00 |
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Ross Thompson
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1126135b80
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minro change. comments about needed changes in dcache.
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2021-12-19 13:53:02 -06:00 |
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David Harris
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f201af4bb7
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Renamed zero to eq in flag generation
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2021-12-19 11:49:15 -08:00 |
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David Harris
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406f129bed
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Controller fix
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2021-12-18 22:08:23 -08:00 |
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David Harris
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67577d7c91
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Renamed RD1D to R1D, etc.
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2021-12-18 21:26:00 -08:00 |
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David Harris
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721d0b5bcf
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Simplified shifter right input
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2021-12-18 10:25:40 -08:00 |
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Ross Thompson
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4daeb6657f
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Merge branch 'tlb_fixes' into main
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2021-12-18 12:24:17 -06:00 |
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David Harris
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7e026f3e78
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Simplified Shifter Right input
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2021-12-18 10:21:17 -08:00 |
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David Harris
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27ec8ff893
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Shared ALU mux input for shifts
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2021-12-18 10:08:52 -08:00 |
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David Harris
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eed2765033
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Factored out common parts of shifter
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2021-12-18 10:01:12 -08:00 |
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David Harris
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53baf3e787
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Cleaning shifter
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2021-12-18 09:43:09 -08:00 |
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David Harris
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ebcffcdebd
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Moved W64 truncation after result mux
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2021-12-18 09:27:25 -08:00 |
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David Harris
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23c6b6370f
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Forwarding logic factoring
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2021-12-18 05:40:38 -08:00 |
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David Harris
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10dfefa8ad
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Simplified FWriteInt interfaces by merging into RegWrite
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2021-12-18 05:36:32 -08:00 |
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David Harris
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0f319b45c1
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Do File cleanups
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2021-12-17 17:45:26 -08:00 |
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Ross Thompson
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bbd1332353
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Merge remote-tracking branch 'origin/tlb_fixes' into main
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2021-12-17 14:40:29 -06:00 |
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Ross Thompson
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a11597b6bd
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Added more debugging code for FPGA.
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2021-12-17 14:40:25 -06:00 |
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Ross Thompson
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ee81cfff0c
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Possible fix for icache deadlock interaction with hptw.
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2021-12-17 14:38:25 -06:00 |
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David Harris
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d9f569afe1
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Added irscv-arch-test and rsicv-isa-sim
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2021-12-15 12:38:35 -08:00 |
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David Harris
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aebd746e71
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Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
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2021-12-15 12:10:45 -08:00 |
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David Harris
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4e35736e90
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IEU cleanup:
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2021-12-15 11:38:26 -08:00 |
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Ross Thompson
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6d2a4b8354
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Oups missed files in the last commit.
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2021-12-15 10:25:08 -06:00 |
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Ross Thompson
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21b13fc237
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Reverted 23Mhz to 10Mhz. The flash card can't work at that speed.
added icache debugging signals.
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2021-12-15 10:24:29 -06:00 |
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David Harris
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865d5ce0b1
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Renamed dtim->ram and boottim ->bootrom
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2021-12-14 13:43:06 -08:00 |
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David Harris
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d7e78f8707
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-14 13:05:47 -08:00 |
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David Harris
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ecce1e62ee
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changed ideal memory to MEM_DTIM and MEM_ITIM
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2021-12-14 13:05:32 -08:00 |
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Ross Thompson
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9886ed3028
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Comments for dcache and icache refactoring.
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2021-12-14 14:46:29 -06:00 |
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David Harris
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8dcf2c65f2
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renamed rv32/64g to rv32/64gc in configuration
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2021-12-14 11:22:00 -08:00 |
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David Harris
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0e9fe6c214
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-14 11:15:58 -08:00 |
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David Harris
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2d24230093
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ALU and datapath cleanup
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2021-12-14 11:15:47 -08:00 |
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Ross Thompson
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997a733a97
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Added patch file for the qemu modifications.
Added instructions for building and installing qemu.
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2021-12-13 18:36:00 -06:00 |
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Ross Thompson
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e7052d1ccf
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-13 18:30:14 -06:00 |
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Ross Thompson
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ca404746ec
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Updated .gitignore file to hide fpga outputs.
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2021-12-13 18:30:10 -06:00 |
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Ross Thompson
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af9f97454d
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Cleaned up fpga synthesis script.
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2021-12-13 18:26:54 -06:00 |
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Ross Thompson
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30941c073a
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Possible fix for icache and ptw interlock deadlock issue.
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2021-12-13 18:23:43 -06:00 |
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Ross Thompson
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2d662bc4be
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-13 17:16:20 -06:00 |
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Ross Thompson
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81da8b8d2a
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Formating changes to cache fsms.
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2021-12-13 17:16:13 -06:00 |
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Ross Thompson
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4d6d72a082
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Fixed some typos in the dcache ptw interaction documentation.
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2021-12-13 15:47:20 -06:00 |
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David Harris
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55f3979b67
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-13 07:57:49 -08:00 |
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David Harris
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2039752740
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Simplified ALU and source multiplexers pass tests
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2021-12-13 07:57:38 -08:00 |
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kwan
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8f79a12cbb
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priviledge .* removed, passed regression
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2021-12-13 00:34:43 -08:00 |
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kwan
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f0e425e4ea
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test
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2021-12-13 00:31:51 -08:00 |
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kwan
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a365e86197
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priviledge .* fixed, passed local regression
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2021-12-13 00:22:01 -08:00 |
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Kevin
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03274de97c
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-12 17:53:41 -08:00 |
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Kevin
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98420cb988
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dot stars conversions on the rest of the testbenches
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2021-12-12 17:53:26 -08:00 |
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Ross Thompson
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051dd7d09d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-12 17:33:29 -06:00 |
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Ross Thompson
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395766219b
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Revert "Privilige .*s removed"
This reverts commit 82bab8e90e.
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2021-12-12 17:31:57 -06:00 |
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Ross Thompson
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f758a53247
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Revert "Priviledged .* removed"
This reverts commit a95efea0b3.
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2021-12-12 17:31:39 -06:00 |
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