8 Commits

Author	SHA1	Message	Date
Ross Thompson	290430cda8	Moved the sub cache line read logic to lsu/ifu.	2022-02-04 20:42:53 -06:00
David Harris	a6708ed887	cache cleanup	2022-02-03 15:36:11 +00:00
David Harris	da8819d64b	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
Ross Thompson	4422e2f91c	Repaired wavefile and fixed modelsim warning.	2022-01-31 12:34:17 -06:00
Ross Thompson	f4e62bcb54	Cleanup busdp.	2022-01-31 12:17:07 -06:00
Ross Thompson	9cd502d0af	Encapsulated dtim.	2022-01-31 11:23:55 -06:00
Ross Thompson	c939eb20eb	Removed unused signals in the LSU.	2022-01-31 10:35:35 -06:00
Ross Thompson	a4f6653cd8	Encapsulated the bus data path into a separate module.	2022-01-31 10:15:48 -06:00